
PM5317 SPECTRA-9953 Telecom Standard Product Data Sheet
Release
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2000741, Issue 5
351
Register 0190H: CSTRI Control
Bit
Type
Function
Default
Bit 15
R/W
Reserved
0
Bit 14
R/W
Reserved
0
Bit 13
R/W
Reserved
0
Bit 12
R/W
Reserved
0
Bit 11
R/W
Reserved
0
Bit 10
R/W
Reserved
1
Bit 9
R/W
TXREF_CEN
0
Bit 8
R/W
Reserved
0
Bit 7
R/W
Reserved
0
Bit 6
R/W
Reserved
0
Bit 5
R/W
Reserved
0
Bit 4
R/W
CSU_ENB
0
Bit 3
R/W
CSU_RSTB
1
Bit 2
Unused
X
Bit 1
Unused
X
Bit 0
R/W
Reserved
1
CSU_RSTB
The CSU_RSTB bit drives a software-reset signal that forces the CSU1250 into a reset. It is
joined with the CSTRI ARB input signal (using an AND gate) and is then connected to the
CSU_ARSTB output pin. For normal operation, it is held at logic ‘1’. To properly reset the
CSU, the CSU_RSTB pin should be held low for at least 1 ms. Both the CSU_ENB bit and
the CSU_IDDQ bit must be set to “0” during reset of the CSU.
CSU_ENB
The active low CSU enable control signal (CSU_ENB) bit can be used to force the
CSU1250 into low power configuration if it is set to logic 1. For normal operation, it is set
to logic 0. CSU_ENB (and CSU_IDDQ) must also be set to “0” while resetting the CSU.
It is connected to the CSU_ENB pin.
TXREF_CEN
The TXLVREF chopper stabilization enable (TXREF_CEN) bit is connected to the
TXREF_CEN output pin. It determines whether or not the offset correction circuitry
(clocked by CCLK) is enabled in the TXLVREF_1250.