M68HC11
REFERENCE MANUAL
ON-CHIP MEMORY
MOTOROLA
4-9
can result from repeated read operations. 2) Erase operations normally take less time
than programming operations. 3) The most common EEPROM failure (write ones) is
an unintended bit change from one to zero during programming of $FF data. This fail-
ure occurs during endurance testing as the part approaches wear-out (typically after
tens of thousands of write-erase cycles). 4) Retention failures result in programmed
zeros reverting to ones due to leakage of the floating-gate charge. 5) Ones never re-
vert to zeros without an explicit programming operation (though the programming op-
eration need not involve any zeros in the pattern being programmed).
Figure 4-7 Reading an EEPROM Byte
EEPROM programming and erasure involve the movement of charge through a thin
oxide layer. This charge movement requires a relatively large field to be present for a
significant length of time (milliseconds). Noise is not likely to cause individual bits to
change state. Most failures of the EEPROM involve breakdowns due to the relatively
high voltages or to an oxide degradation phenomenon (trapped charge). After many
cycles of programming and erasure, charge may become trapped in the thin oxide lay-
ers isolating the floating gate. This trapped charge causes programming and erase op-
erations to take longer as the amount of trapped charge increases. When the cell fails
to program to zero in the allotted time, it is worn out. In many cases, these bits can still
be programmed and erased provided the program and erase times are increased. The
useful life of an EEPROM byte cannot be extended very far by extending the program-
ming time because a worn bit exhibits a reduced ability to retain valid zeros for very
long time periods.
4.3.3 Systems Operating below 2-MHz Bus Speed (E Clock)
The on-chip charge pump that generates V
PP
from V
DD
uses MOS capacitors, which
are relatively small in value. The efficiency of this charge pump and its drive capability
are affected by the level of V
DD
and the frequency of the driving clock. The load de-
pends on the number of bits being programmed or erased and capacitances in the EE-
PROM array. Effective array load capacitances are influenced to some degree by the
data in the array.
The clock source driving the charge pump is software selectable. When the clock se-
ARRAY GROUND
7
VDD
6
5
4
3
2
1
0
VSS
VSS
PRECHARGE THEN SENSE