M68HC11
REFERENCE MANUAL
ASYNCHRONOUS SERIAL COMMUNICATIONS INTERFACE
MOTOROLA
9-1
SECTION 9
ASYNCHRONOUS SERIAL COMMUNICATIONS INTERFACE
This section describes the universal asynchronous receiver transmitter (UART) type
serial communications interface (SCI) system, which is one of two independent serial
I/O subsystems in the M68HC11. The other serial I/O subsystem (called SPI) provides
for high-speed synchronous serial communication to peripherals or other microcontrol-
ler units (MCUs), usually located on the same printed circuit board as the M68HC11.
This SCI system can be used to connect a CRT terminal or personal computer to the
MCU, or several widely distributed MCUs can use their SCI subsystems to form a se-
rial communication network.
9.1 General Description
The SCI is a full-duplex UART-type asynchronous system, using standard non-return-
to-zero (NRZ) format (one start bit, eight or nine data bits, and a stop bit). An on-chip
baud rate generator derives standard baud-rate frequencies from the MCU oscillator.
Both the transmitter and the receiver are double buffered; thus, back-to-back charac-
ters can be handled easily, even if the central processing unit (CPU) is delayed in re-
sponding to the completion of an individual character. The SCI transmitter and
receiver are functionally independent but use the same data format and baud rate. In
this reference manual, baud rate and bit rate are used synonymously. The user will
usually have to provide external level-shifter buffers to translate the RS232 or RS422
levels (typically
±
12 V) to the 0- to 5-V logic levels used by the MCU.
This SCI receiver includes a number of advanced features to assure high-reliability
data reception and to assist development of efficient communications networks. The
M68HC11 resynchronizes the receiver bit clock on all one-to-zero transitions in the bit
stream rather than just at the beginning of the start bit time; therefore, differences in
baud rate between the sending device and the MCU are not as likely to cause recep-
tion errors. Three logic-level samples are taken near the middle of each bit time, and
majority logic decides the sense for the bit. Even if noise causes one of these samples
to be incorrect, the bit will still be received correctly. The receiver also has the ability
to enter a temporary standby mode (called receiver wake up) to ignore messages in-
tended for a different receiver. Logic automatically wakes up the receiver in time to see
the first character of the next message. This wake-up feature greatly reduces CPU
overhead in multi-drop SCI networks.
The SCI transmitter can produce queued characters of idle (whole characters of all
logic one) and break (whole characters of all logic zero). In addition to the usual trans-
mit data register empty (TDRE) status flag, this SCI also provides a transmit complete
(TC) indication that can be used in applications with a modem.
9.1.1 Transmitter Block Diagram
Figure 9-1
is a block diagram of the transmitter section of the SCI subsystem. The de-