
MOTOROLA
2-26
PINS AND CONNECTIONS
M68HC11
REFERENCE MANUAL
voltage increases, the thick-field protection device begins to conduct more current to
the die substrate, which is V
SS
. There should be some external series impedance be-
tween the pin and the input voltage source if the MCU will be used in a detrimental
environment. If the input voltage is increased even further, the protection device [2] will
avalanche, and the pin voltage will eventually fold back (typically to about 7 to 12 V).
Under these conditions, a parasitic bipolar transistor, which is not obvious from the
MOS schematic, is turned on and is holding the pin at the 7-volt level. This avalanche
is still normally not destructive to the pin. Since the foldback clamp level is relatively
low impedance, the pin voltage cannot be raised further without supplying a large cur-
rent. If the offending voltage source is increased to increase the pin current, the pin
circuitry will be damaged (specified limit is 25 mA, typically takes more than 100 mA).
Gate oxides in these inputs are not intended to be exposed to voltages above 7 V for
any significant amount of time. With the HCMOS processing used in the
MC68HC11A8, a latchup failure is unlikely unless legal drive limits are grossly exceed-
ed.
2.4.4 Internal Circuitry — Analog Input-Only Pin
Figure 2-16
shows the MOS circuitry associated with an analog input-only pin. This
MOS logic is similar to that for a digital input-only pin except for the addition of the an-
alog multiplexer [5] and the extra N-channel device below the buffer. The N-channel
device [5] acts as an analog multiplexer and affects the behavior of an analog input pin
when exposed to negative voltages. The N-channel device [4] allows the analog input
pins to be driven by intermediate levels without causing the noise and current normally
associated with the input buffer when its input is at a midsupply level. This device is
only turned on for half an E-clock cycle during a digital read of port E. Since the analog
input pins (including the V
REF
pins) are only connected to N-channel devices and high-
impedance gates, these pins can be driven with levels above V
DD
without the usual
fear of latchup. This aspect is important because the analog reference supply is typi-
cally independent of the V
DD
supply for noise isolation reasons.
An analog input pin (see
Figure 2-16
) responds very much like a digital input to illegal
levels except that negative levels at the pin can affect A/D operations. The analog
functions associated with these pins also present some special challenges to protec-
tive interface circuits. Although the N-channel devices [4] eliminates the need for ex-
ternal pull-up or pulldown resistors on unused port E pins, a conservative designer
would still terminate these pins to help prevent static damage.