MOTOROLA
10-30
MAIN TIMER AND REAL-TIME INTERRUPT
M68HC11
REFERENCE MANUAL
As long as an output-compare function is configured to change a pin state or to gen-
erate an interrupt, the action occurs every time the timer-count value matches the
compare register (not just the first time a match occurs). To generate a single interrupt
after some delay, read the TCNT register, add a value corresponding to the desired
delay, write that value to the output-compare register, and write the appropriate con-
trols to enable the interrupt. When the interrupt occurs, write the appropriate controls
to disable the interrupt, or another interrupt will occur as soon as the free-running timer
rolls around to the output-compare register value again.
The following registers and paragraphs explain the output-compare status flags and
the local interrupt enable control bits for the output-compare functions.
OCxI, OCxF — Output Compare Interrupt Enables and Output Compare Flags (x= 1, 2,
3, 4, or 5)
The OCxF status bit is automatically set to one each time the corresponding output-
compare register matches the free-running timer. This status bit is cleared by writing
to the TFLG1 register with a one in the corresponding data bit position. The OCxI con-
trol bit allows the user to configure each output-compare function for polled or inter-
rupt-driven operation but does not affect the setting or clearing of the corresponding
OCxF bit. When OCxl is zero, the corresponding output-compare interrupt is inhibited,
and the output compare is operating in a polled mode. In this mode, the OCxF bit must
be polled (read) by user software to determine when a match has been detected.
Bit 7
Bit 15
Bit 7
6
—
—
5
—
—
4
—
—
3
—
—
2
—
—
1
—
—
Bit 0
Bit 8
Bit 0
$1016
$1017
TOC1
$1018
$1019
Bit 15
Bit 7
—
—
—
—
—
—
—
—
—
—
—
—
Bit 8
Bit 0
TOC2
$101B
Bit 7
—
—
—
—
—
—
Bit 0
$101C
$101D
Bit 15
Bit 7
—
—
—
—
—
—
—
—
—
—
—
—
Bit 8
Bit 0
TOC4
$101E
$101F
Bit 15
Bit 7
—
—
—
—
—
—
—
—
—
—
—
—
Bit 8
Bit 0
TOC5
TMSK1 —
Timer Interrupt Mask Register 1
$1022
BIT 7
OC1I
0
6
5
4
3
2
1
BIT 0
IC3I
0
OC2I
0
OC3I
0
OC4I
0
OC5I
0
IC1I
0
IC2I
0
RESET:
TFLG1 —
Timer Interrupt Flag Register 1
$1023
BIT 7
OC1F
0
6
5
4
3
2
1
BIT 0
IC3F
0
OC2F
0
OC3F
0
OC4F
0
OC5F
0
IC1F
0
IC2F
0
RESET: