MOTOROLA
5-8
RESETS AND INTERRUPTS
M68HC11
REFERENCE MANUAL
changing the enable bit are designed so the NOCOP bit is very unlikely to be changed
by accident in the end system. The only way to change the enable status of the COP
system is to change the contents of the EEPROM-based CONFIG register. Even after
the NOCOP bit is changed, the MCU must be reset before the new status becomes
effective. In the special test and bootstrap operating modes, the COP system is initially
inhibited by the disable resets (DISR) control bit in the TEST1 register. The DISR bit
can be written to zero to enable COP resets while the MCU is in special test or boot-
strap operating mode.
The COP time-out period is set by the COP timer rate control bits (CR1 and CR0) in
the configuration options (OPTION) register. After reset, these bits are both zero,
which selects the fastest time-out period. The MCU internal E clock is first divided by
2
15
before it enters the COP watchdog system. The CR1 and CR0 bits control a further
scaling factor for the watchdog timer (see
Table 5-3
). The columns at the right of the
table show the resulting watchdog time-out periods for three typical oscillator frequen-
cies. In normal operating modes, these bits can only be written once, and that write
must be within 64 bus cycles after reset.
The COP timer must be reset by a software sequence prior to time-out to avoid a COP
reset. The software COP reset is a two-step sequence. The first step is to write $55 to
the COPRST register to arm the COP timer-clearing mechanism. The second step is
to write $AA to the COPRST register, which clears the COP timer. Any number of in-
structions can be performed between these two steps as long as both steps are per-
formed in the correct sequence before the timer times out. This reset sequence is
sometimes referred to as servicing the COP timer.
Since the COP timer is based on the MCU clock, the COP watchdog cannot detect er-
rors that cause the MCU clock to stop. The clock monitor system (see
5.2.3 Clock
Monitor Reset
) can be used as a backup for COP to force a system reset if the MCU
clocks stop.
Placing the COP service instructions in an interrupt service routine is bad practice. In
such a case, the interrupt could occur often enough to keep the COP system satisfied
even if the main-line program was no longer functioning.
The implementation of the COP timer causes a tolerance on the time-out period. The
Table 5-3 Watchdog Rates vs. Crystal Frequency
CR1
CR0
E
÷
2
15
Divided By
Crystal Frequency
8 MHz
Nominal Time-Out
16.384 ms
65.536 ms
262.14 ms
1.049 s
2 MHz
Bus Frequency (E clock)
2
23
Hz
4 MHz
0
0
1
1
0
1
0
1
1
4
15.625 ms
62.5 ms
250 ms
1 s
2.1 MHz
32.768 ms
131.07 ms
524.29 ms
2.1 s
1 MHz
16
64