MOTOROLA
1-2
GENERAL DESCRIPTION
M68HC11
REFERENCE MANUAL
speeds with the low power and high noise immunity of CMOS. On-chip memory sys-
tems include 8 Kbytes of read-only memory (ROM), 512 bytes of electrically erasable
programmable ROM (EEPROM), and 256 bytes of random-access memory (RAM).
Major peripheral functions are provided on-chip. An eight-channel analog-to-digital (A/
D) converter is included with eight bits of resolution. An asynchronous serial commu-
nications interface (SCI) and a separate synchronous serial peripheral interface (SPI)
are included. The main 16-bit, free-running timer system has three input-capture lines,
five output-compare lines, and a real-time interrupt function. An 8-bit pulse accumula-
tor subsystem can count external events or measure external periods.
Self-monitoring circuitry is included on-chip to protect against system errors. A com-
puter operating properly (COP) watchdog system protects against software failures. A
clock monitor system generates a system reset in case the clock is lost or runs too
slow. An illegal opcode detection circuit provides a non-maskable interrupt if an illegal
opcode is detected.
Two software-controlled power-saving modes, WAIT and STOP, are available to con-
serve additional power. These modes make the M68HC11 Family especially attractive
for automotive and battery-driven applications.
Figure 1-1
is a block diagram of the MC68HC11A8 MCU. This diagram shows the ma-
jor subsystems and how they relate to the pins of the MCU. In the lower right-hand cor-
ner of this diagram, the parallel I/O subsystem is shown inside a dashed box. The
functions of this subsystem are lost when the MCU is operated in expanded modes,
but the MC68HC24 port replacement unit can be used to regain the functions that were
lost. The functions are restored in such a way that the software programmer is unable
to tell any difference between a single-chip system or an expanded system containing
the MC68HC24. By using an expanded system containing an MC68HC24 and an ex-
ternal EPROM, the user can develop software intended for a single-chip application.
1.2 Programmer’s Model
In addition to executing all M6800 and M6801 instructions, the M68HC11 instruction
set includes 91 new opcodes. The nomenclature M68xx is used in conjunction with a
specific CPU architecture and instruction set as opposed to the MC68HC11xx nomen-
clature, which is a reference to a specific member of the M68HC11 Family of MCUs.
Figure 1-2
shows the seven CPU registers available to the programmer. The two 8-
bit accumulators (A and B) can be used by some instructions as a single 16-bit accu-
mulator called the D register, which allows a set of 16-bit operations even though the
CPU is technically an 8-bit processor.
The largest group of instructions added involve the Y index register. Twelve bit manip-
ulation instructions that can operate on any memory or register location were added.
The exchange D with X and exchange D with Y instructions can be used to quickly get
index values into the double accumulator (D) where 16-bit arithmetic can be used. Two
16-bit by 16-bit divide instructions are also included.