M68HC11
REFERENCE MANUAL
MAIN TIMER AND REAL-TIME INTERRUPT
MOTOROLA
10-37
*** initialization - (see full listing) ***
c217 86 50
[2]
c219 a7 20
[4]
c21b 86 70
[2]
c21d a7 0c
[4]
c21f 5f
[2]
c220 b6 d0 03
[4]
c223 81 32
[2]
c225 23 02
[3]
c227 cb 40
[2]
c229 b6 d0 04
[4]
ARNZ61
c22c 81 32
[2]
c22e 23 02
[3]
c230 cb 20
[2]
c232 e7 0d
[4]
ARNZ62
* Calculate period & duty cycle as cycle count offsets
c234 b6 d0 02
[4]
LDAA
PWMP1P
c237 c6 64
[2]
LDAB
#100
c239 3d
[10]
MUL
c23a fd d0 1f
[5]
STD
PWMPER
c23d ed 16
[5]
STD
TOC1,X
c23f b6 d0 03
[4]
LDAA
PWMDC1
c242 8d 12
[6]
BSR
CALOFF
c244 ed 18
[5]
STD
TOC2,X
c246 b6 d0 04
[4]
LDAA
PWMDC2
c249 0d 0b
[6]
BSR
CALOFF
c24b ed 1a
[5]
STD
TOC3,X
c24d 86 80
[2]
LDAA
#$80
c24f a7 23
[4]
STAA
TFLG1,X
c251 a7 22
[4]
STAA
TMSK1,X
c253 0e
[2]
CLI
c254 20 fe
[3]
BRA
*
***
* SV6OC1 - Output Compare 1 service routine
***
c269 ce 10 00
[3]
SV6OCI
LDX
#REGBAS
c26c a6 0d
[4]
LDAA
OC1D,X
c26e 88 10
[2]
EORA
#%00010000
c270 a7 0d
[4]
STAA
OC1D,X
c272 0c 18
[5]
LDD
TOC2,x
c274 f3 d0 1f
[6]
ADDD
PWMPER
c277 ed 18
[5]
STD
TOC2,X
c279 ec 1a
[5]
LDD
TOC3,x
c27b f3 d0 1f
[6]
ADDD
PWMPER
c27e ed 1a
[5]
STD
TOC3,X
c280 ec 16
[5]
LDD
TOC1,X
c282 f3 d0 1f
[6]
ADDD
PWMPER
c285 ed 16
[5]
STD
TOC1,X
c287 1d 23 7f
[7]
BCLR
TFLG1,X $7F Clear OC1F
c28a 3b
[12]
RTI
LDAA
STAA
LDAA
STAA
CLRB
LDAA
CMPA
BLS
ADDB
LDAA
CMPA
BLS
ADDB
STAB
#%0l010000
TCTL1,X
#%01110000
OCIM,X
OMx:OLx = 0:1 for toggle
OC2 and OC3 for toggle
OClM6,5, & 4 - 1
Control OC2/PA6, OC3/PA5, & PA4
Build OC1D initial value in B
Check for OC2 duty > or = 50%
If <50% OC1 drives low...
and OC2 toggles high.
Else OC1 driv high/OC2 tog low
Check for OC3 duty > or = 50%
If <50% OC1 drives low...
and OC3 toggles high.
Else OC1 driv high/OC3 tog low
Store starting value for OC1D
PWMDC1
#50
ARNZ61
#%01000000
PWMDC2
#50
ARNZ62
#%00100000
OC1D,X
1% of period
100 * PWMP1P = PWMPER
Store period
Start with TCNT = PWMPER
Calculate offset for OC2
Adj duty and calc offset
Schedule first OC2 toggle
Calculate offset for OC3
Adj duty and calc offset
Schedule first OC3 toggle
Finish initialization
Clear any old OC1 flag
Enable OC1 interrupt
PWMs driven by OC1 interrupts
Point to register block
Change state of PA4 at next OC1
Inverts OClD4 (PA4 pin control)
Update OC1 automatic pattern
Get last OC2 compare value
Add count equiv to period
Update OC2 (schedule next OC2)
Get last OC3 compare value
Add count equiv to period
Update OC3 (schedule next OC3)
Get last OC1 compare value
Add count equiv to period
Update OC1 (schedule next OCl)
** Return from OC1 service **
Figure 10-12 Producing Two PWM Outputs with OC1, OC2, and OC3
The larger upper portion of this program is executed only once to set up and to start
the PWM outputs. After this initial setup, the PWM signals are free running and are
controlled by OC1 interrupts only. When an OC1 interrupt occurs, a value equal to the
period is added to each of the output-compare registers (TOC1, TOC2, and TOC3).
When this OC1 service routine is enabled, the PWM outputs will have been forced to
their active level by the OC1 match that requested the interrupt. When this service rou-
tine is done, OC1 is set to start the next PWM period; OC2 and OC3 are set to termi-
nate the current PWM pulse. The PWM pulses, which are known to be at least 50