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參數(shù)資料
| 型號(hào)： | MC68HC11A8 |
| 廠商： | Motorola, Inc. |
| 元件分類： | 8位微控制器 |
| 英文描述： | 8-Bit Microcontroller(8位微控制器) |
| 中文描述： | 8位微控制器（8位微控制器） |
| 文件頁(yè)數(shù)： | 101/512頁(yè) |
| 文件大?。?/td> | 4071K |
| 代理商： | MC68HC11A8 |
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M68HC11
REFERENCE MANUAL
ON-CHIP MEMORY
MOTOROLA
4-17
nates a write-erase cycle. Another method called ‘selective-write’ has been proposed
but has not been tested and characterized enough to be sure it will work in all cases.
In this method, the data pattern used in the programming operation would have ones
in all positions except the bits that are zeros in the new value but were ones in the pre-
vious value. The idea in this method is to avoid reprogramming bits already pro-
grammed. The benefits are theoretical and have not been proven. Although both of
these methods (write-more-zeros and selective-write) appear to work correctly in lab-
oratory experimentation, the combination of the two methods is known to fail. An ex-
ample of a failing combination would be to attempt to program $FC to a location that
previously contained the value $0D in an attempt to change the location to the value
$0C. In this case, bit 1 follows the write-more-zeros method; whereas, bits [4:7] follow
the selective-write method. A detailed explanation of this case is given in
4.4.7 Soft-
ware Methods to Extend Life Expectancy
.
System software should be partitioned so that data and programs in EEPROM will
never be used while an EEPROM programming or erase operation is in progress.
When the EELAT control bit is set to one at the beginning of a program or erase oper-
ation, the EEPROM is electronically removed from the MCU memory map; thus, it is
not accessible during the programming or erase operation. Since it is possible to per-
form other tasks while the 10-ms EEPROM operation is in progress, it is fairly common
to start the operation and return to the main program until the 10 ms is completed. If a
routine in the main program or an interrupt tries to access a value in EEPROM while
a programming operation is in progress, that operation will fail since the EEPROM is
temporarily inaccessible.
In an interrupt-driven system, it may be possible for an asynchronous interrupt to occur
in the middle of an EEPROM programming or erase operation. Such an interrupt can
cause the programming or erase operation to extend beyond the normal 10-ms period.
A small extension of the programming or erase time will not damage the EEPROM or
compromise the intended operation. Repeated extension or long extensions may in-
volve a slight acceleration of write-erase wear-out because wear-out is related to the
length of time high voltages are present in the EEPROM array. The most significant
effects of wear-out occur near the beginning of a program or erase operation because
the charge tunneling activity follows an exponential decay curve, which implies that ex-
tensions of programming time should have very little effect on the EEPROM cell. An-
other risk, which is difficult to quantify, is the possibility of high-voltage breakdown of
row and column devices due to the presence of programming voltage. If programming
and erase times are extended, these devices are exposed to high voltages for a longer
time; thus, there is increased risk that a breakdown might occur.
In some systems, an EEPROM programming or erase operation could be in progress
when a power failure or reset occurs, which presents the possibility that an EEPROM
location might be corrupt or unreliable due to an incomplete programming operation.
A way to avoid this problem is to design the system so power failures generate a non-
maskable interrupt prior to complete loss of power. This interrupt would allow EE-
PROM operations to be completed prior to system shutdown. Other systems may
have battery backup of RAM so programming status could be maintained in this mem-
ory. Upon reset, this status (in RAM) could be checked, and any operation that was in
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