M68HC11
REFERENCE MANUAL
RESETS AND INTERRUPTS
MOTOROLA
5-1
SECTION 5
RESETS AND INTERRUPTS
Reset and interrupt operations are often discussed together because they share the
common concept of vector fetching to force a new starting point for further central pro-
cessing unit (CPU) operations. The reset structure in the MC68HC11A8, which is quite
different from other MCUs, is presented in this section. This reset system can generate
a reset output if reset-causing conditions are detected by internal systems. The on-
chip electrically erasable programmable read-only memory (EEPROM) also places
extra demands on external circuitry connected to the RESET pin.
The MC68HC11A8 includes 18 separate interrupt sources. On-chip peripheral sys-
tems generate maskable interrupts, which are recognized only if the global interrupt
mask bit (I) in the condition code register (CCR) is clear. Three interrupt sources con-
sidered non-maskable will be discussed in detail in this section.
Maskable interrupts are prioritized according to a default arrangement; however, any
one source may be elevated to the highest maskable priority position by a software-
accessible control register. This highest priority interrupt (HPRIO) register may be writ-
ten at any time provided the I bit in the CCR is set.
When interrupt conditions occur in an on-chip peripheral system, an interrupt status
flag is set to indicate the condition. When the user’s program has properly responded
to this interrupt request, the status flag must be cleared. The method of clearing varies
from one system to another, depending on the requirements of the system. The vari-
ous flag clearing methods and considerations are discussed in
5.7 Interrupts from In-
ternal Peripheral Subsystems
.
5.1 Initial Conditions Established During Reset
Reset is used to force the microcontroller unit (MCU) to assume a set of initial condi-
tions and to begin executing instructions from a predetermined starting address. For
most practical applications, the initial conditions take effect almost immediately after
applying an active-low level to the RESET pin. Some reset conditions cannot take ef-
fect until/unless a clock is applied to the external clock input (EXTAL) pin. One exam-
ple is port B, which acts as an address output port in the expanded modes and as a
general-purpose output port in the single-chip modes. During reset in expanded mode,
these pins would be $FF because this is the high-order half of $FFFE. During reset in
single-chip mode, these pins would be $00. Since the mode pins are pipelined into the
MCU, a clock is needed for the MCU to recognize the mode selected.
If no clock is present, the port B pins could be in the wrong state due to the inability of
the MCU to recognize the correct mode of operation. If no clock is present, the MCU
cannot advance out of the reset condition since internal reset is a clocked sequence;
thus, the MCU cannot advance past the first step of this sequence. Even with no clock
present, a RESET signal will cause some changes. Most important, an unclocked RE-