MOTOROLA
I-2
M68HC11
REFERENCE MANUAL
Condition Code
2-17, 3-12, 5-1, 5-23, 6-1, 6-2, 6-4, 6-12,
6-17, 8-7, 10-21, 11-2, 11-9
Condition Code Register (CCR)
2-17, 2-18, 5-1, 5-2, 5-9,
5-11, 5-21, 5-23, 6-4, 6-5, 6-11, 8-7, 8-9, 10-21,
10-28
Condition Code Register Instructions (Instructions)
6-17
CONFIG Register (Registers)
1-6, 2-1, 2-3, 2-16, 2-33,
3-3, 3-4, 3-10, 3-11, 3-19, 3-23, 4-1, 4-2, 4-4,
4-13, 4-18, 4-23, 5-2, 5-3, 5-4, 5-7, 5-8
Configuration
2-28, 3-13, 4-1, 4-8, 4-18, 5-2, 5-3, 5-4, 5-8,
5-25, 7-2, 7-5, 7-15, 7-28, 7-43, 8-6, 8-8, 8-9,
8-10, 8-12, 9-6, 9-15, 10-11, 10-35
Configuration Mechanism
3-3
Conversion Sequence,
A/D 12-3, 12-4, 12-13, 12-18,
12-20
COP Watchdog
3-5, 3-13, 5-3, 5-4, 5-5, 5-6, 5-7, 10-5,
10-7, 10-13
COPRST Register (Registers)
5-8
Counter
4-26, 5-5, 5-11, 5-20, 5-24, 6-3, 6-4, 6-10, 8-11,
9-7, 9-8, 10-1, 10-5, 10-11, 10-15, 10-16, 10-35,
10-38, 10-39, 10-40, 11-1, 11-6, 11-7, 11-8,
11-9, 11-10, 11-11
Counter Bypass
10-11
CPHA (Bit in SPCR)
8-2, 8-3, 8-8, 8-10, 8-11
CPOL (Bit in SPCR)
8-1, 8-2, 8-8, 8-12, 8-13
CPU
1-2, 2-20, 2-21, 3-1, 3-7, 3-12, 4-3, 5-1, 5-2, 5-11,
5-21, 5-23, 5-24, 5-27, 6-1, 6-6, 6-10, 6-11,
7-11, 7-17, 9-1, 9-15, 10-19, 10-21, 11-2, 11-9
CR0 (Bit in OPTION)
3-9, 5-8, 10-14
CR1 (Bit in OPTION)
3-9, 5-8, 10-14
CR1,CR0 (Bits in OPTION)
3-9, 3-10
Crystal Oscillator
2-11, 2-15
CSEL (Bit in OPTION)
3-9, 4-10, 12-13
CWOM (Bit in PIOC)
5-2, 7-2, 7-18, 7-46
–D–
Data Direction Registers (Registers)
7-5
Data Direction, I/O
5-2, 7-1, 7-2, 7-5, 7-25, 7-26, 8-4, 8-6,
8-7, 9-5, 9-18, 10-35, 11-2, 11-4
Data Sampling
9-20, 9-25
Data Testing Instructions (Instructions)
6-11
DDRA7 (Bit in PACTL)
7-1, 7-10, 10-35, 11-2, 11-4
DDRC Register (Registers)
5-2, 7-2, 7-18, 7-45
DDRD Register (Registers)
2-20, 7-2, 7-5, 7-25, 8-5, 8-6,
8-9, 9-5, 9-6, 9-18, 9-19, 9-31
Derivatives
1-4, 2-37
Disable Resets
3-13, 5-8
DISR (Bit in TEST1)
3-11, 3-12, 3-13, 5-8, 5-9
Divide Instruction (Instructions)
1-2, 2-14, 5-8, 5-9, 5-12,
6-1, 6-5, 6-11, 6-13, 9-7, 9-8, 9-30, 10-6, 10-25,
11-1, 11-2, 11-9, 11-10, 12-12, 12-16
DLY (Bit in OPTION)
3-9, 4-12
Double Accumulator (AD) 1
-2, 6-1, 6-3
Double-Buffered Receive
9-20
Double-Byte Read
10-5, 10-16, 10-40
Double-Byte Write
10-29
DWOM (Bit in SPCR)
2-20, 3-16, 3-17, 7-3, 7-26, 8-6,
8-7, 8-10, 9-7, 9-19
–E–
E
3-10
Edge Sensitive Input
5-25
EDGxA (Bits in TCTL2)
10-17, 10-18
EDGxB (Bits in TCTL2)
10-17, 10-18
EELAT (Bit in PPROG)
4-10, 4-11, 4-17
EEON (Bit in CONFIG)
3-5, 4-4
EEPGM (Bit in PPROG)
4-10, 4-12, 10-4
EEPROM
1-2, 1-6, 2-2, 2-3, 2-16, 2-17, 2-18, 2-31, 2-33,
3-1, 3-3, 3-4, 3-5, 3-10, 3-11, 3-20, 4-1, 4-2, 4-4,
4-5, 4-6, 4-7, 4-8, 4-9, 4-10, 4-11, 4-12, 4-14,
4-16, 4-18, 4-19, 4-20, 4-23, 5-1, 5-2, 5-8, 5-25,
10-4, 10-31, 12-14
EEPROM Cell
4-6, 4-7, 5-2, 5-3
EGA (Bit in PIOC)
5-2, 7-20, 7-24, 7-43, 7-47
ERASE (Bit in PPROG)
4-11, 4-12, 4-13
Erase-Before-Write
4-21, 4-22, 4-23, 4-24
EVEN (Bit in PPROG)
4-11, 11-6
Expanded Mode
1-2, 2-7, 2-8, 2-18, 2-20, 2-21, 2-33,
2-38, 4-15, 5-1, 5-26, 7-1, 7-11, 7-12
EXTAL Pin (Pins)
2-11, 2-22, 5-1, 5-7
Extended Addressing
6-3, 6-7
External bus clock output
2-21, 2-33, 4-9, 4-10, 5-8, 7-11,
7-25, 7-43, 10-6, 10-42, 11-2, 12-13
External Reset
5-6, 5-10
Extra Stop Bit
9-9, 9-15
–F–
FCM (Bit in TEST1)
3-12, 3-13
FCOP (Bit in TEST1)
3-12, 3-13
FE (Bit in SCSR)
2-37, 5-3, 6-10, 9-6, 9-11, 9-28, 11-7
Flag Clearing
5-1, 10-12
Floating Gate
4-6, 4-7, 4-21, 4-25
Floating Input
2-22
FOC5-FOC1 (Bits in CFORC)
7-8, 10-39
Fractional Divide Instruction (Instructions)
5-12, 6-13
Framing Error
5-3, 9-6, 9-11, 9-14, 9-24, 9-25
Free-Running Counter
10-1, 10-2, 10-5, 10-15, 10-16,
10-39
–G–
Ground
2-2, 2-7, 2-18, 2-22, 2-23, 2-24, 4-7, 4-8, 7-6,
7-39, 12-17, 12-18
–H–
Half Flip-Flop
9-19
Handshake I/O
2-18, 2-20, 2-38, 5-26, 7-1, 7-2, 7-4, 7-5,
7-12, 7-14, 7-41
Highest Priority Interrupt
2-8, 5-1
HNDS (Bit in PIOC)
5-2, 7-2, 7-15, 7-42, 7-47
HPRIO Register
3-2
HPRIO Register (Registers)
2-8, 2-37, 3-2, 5-1, 5-5, 5-13