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| 型號(hào)： | MC68HC11A8 |
| 廠商： | Motorola, Inc. |
| 元件分類： | 8位微控制器 |
| 英文描述： | 8-Bit Microcontroller(8位微控制器) |
| 中文描述： | 8位微控制器（8位微控制器） |
| 文件頁(yè)數(shù)： | 136/512頁(yè) |
| 文件大小： | 4071K |
| 代理商： | MC68HC11A8 |
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MOTOROLA
5-24
RESETS AND INTERRUPTS
M68HC11
REFERENCE MANUAL
tem initialization has been performed. Part of this minimum initialization would be to
load the stack pointer so it points to an appropriate area of RAM. The I bit is also au-
tomatically set during entry into any interrupt service routine to prevent an infinite
source of interrupts from overwhelming the CPU. Software can also set the interrupt
mask bit to inhibit interrupts during sensitive operations.
The I bit can be cleared by software instructions or during the execution of an RTI in-
struction. In most applications, the I bit remains set during interrupt service routines so
other interrupts will not be honored until a current interrupt service routine finishes (i.e.,
nesting is not permitted). In more unusual applications, it is possible to allow nesting
of interrupts by clearing the I bit during an interrupt service routine. Since this proce-
dure requires much expertise, it should not be attempted by a novice programmer. In
some cases, worst-case interrupt latency can be reduced by allowing interrupt nesting,
but usually the best procedure is to minimize the execution time of interrupt service
routines. Since the overhead associated with interrupt nesting usually violates this pro-
cedure, nesting is not recommended.
The operation of the I bit during service of an interrupt proceeds as follows. When an
enabled interrupt occurs and the I bit is clear, the CPU completes the current instruc-
tion and begins the interrupt response sequence. The current contents of the CPU reg-
isters are pushed onto the stack (stored in stack RAM). The register values are saved
one byte at a time in the following order: PCL, PCH, IYL, IYH, IXL, IXH, ACCA, ACCB,
and CCR. After the CCR value is stacked, the I bit in the CCR is set to inhibit further
interrupts. Next, the vector for the highest priority pending interrupt is fetched, and pro-
cessing continues with execution of the first instruction in the interrupt service routine.
The last instruction in the interrupt service routine is the RTI instruction. This instruc-
tion causes the previously stacked register values to be loaded back into the registers
in reverse order. Since the program counter is restored to its pre-interrupt value, the
next instruction executed will be the instruction that would have been executed if the
interrupt had not occurred.
A common error for new users is to put a set interrupt mask (SEI) instruction at the
beginning of an interrupt service routine and a clear interrupt mask (CLI) instruction
just before the RTI instruction. These instructions should not be used in this way be-
cause they are redundant. The automatic interrupt logic already sets the I bit on the
way into an interrupt and clears the I bit during normal execution of the RTI instruction.
5.5.2 Special Considerations for I-Bit-Related Instructions
There are some special conditions associated with the I bit that require additional con-
sideration. The I bit is actually a sequential logic circuit rather than a simple flip-flop.
When the I bit is set by an SEI or a TAP instruction, interrupts are inhibited immediate-
ly. An interrupt occurring while an SEI instruction is executing will not be honored until
unless the I bit is later cleared. When the I bit is cleared by a CLI or TAP instruction,
the actual clear operation is delayed for one bus cycle so the instruction following the
CLI or TAP will always be executed. This procedure implies that the following loop can
never be interrupted by a maskable interrupt:
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