
MOTOROLA
5-6
RESETS AND INTERRUPTS
M68HC11
REFERENCE MANUAL
In special test and bootstrap modes, MCU vectors are located at $BFC0–$BFFF rath-
er than the normal $FFC0–$FFFF area. The primary reason for this change is to be
sure the reset vector can be supplied from an external source in special test mode.
The normal reset vector is located at $FFFE,FFFF, which can be internal ROM or ex-
ternal memory space (depending on whether the internal ROM is enabled). The spe-
cial test mode reset vector is at $BFFE,BFFF, which is always an external access
independent of other system conditions.
This alternate mapping is important to the operation of bootstrap mode because it al-
lows reset and other vectors to be located within the 192-byte bootloader ROM. As the
MCU comes out of reset in special bootstrap mode, the reset vector is fetched out of
the bootloader ROM, and execution begins at the start of the bootloader program.
While in bootstrap mode, interrupts can be vectored to locations in the bootloaded pro-
gram in RAM rather than vectoring to the routines specified in the internal ROM pro-
gram.
The M68HC11 MCU is capable of distinguishing between an external reset and resets
from the internal COP and clock monitor systems. When the COP watchdog timer
times out or the clock monitor detects a clock failure, the COP and clock monitor status
is temporarily saved. The RESET pin is then driven low for about four E-clock cycles
and is released. Two E-clock cycles later, the RESET input is sampled. If RESET is
high (has risen to logic one within the two cycles since it was released), the source of
reset is presumed to be either the COP or clock monitor system. If RESET is still low,
the source is presumed to be an external reset request, and the temporarily saved sta-
tus from the COP and clock monitor systems is erased. Although there would rarely
be more than one cause for a particular reset sequence, the three reset vectors are
prioritized. If an external reset request drives the RESET pin low for less than four E-
clock cycles, the differentiation logic could assume the source of reset was the internal
COP or clock monitor system; however, as long as neither of these causes was indi-
cated by the temporarily latched status, the normal reset vector would still be used by
default. Although this MCU can differentiate between different reset causes, the most
common implementation would direct all reset vectors to the same initialization soft-
ware, regardless of the cause of reset.
There are four possible sources of reset in the MC68HC11A8. An internal circuit de-
tects the rising edge on V
DD
and initiates a power-on reset. An on-chip COP watchdog
timer monitors proper software execution; if software does not service this timer within
its time-out period, a system reset is generated. Another on-chip circuit monitors the
MCU clock frequency. If the MCU clock stops or is running too slow, a system reset is
generated. Finally, a user can initiate an external reset by momentarily driving the RE-
SET pin low. The COP and clock monitor features can be disabled. The power-on re-
Table 5-2 Reset Vector vs. Cause and MCU Mode
Cause of Reset
POR or RESET Pin
Clock Monitor Fail
COP Watchdog Time-Out
Normal Mode Vector
$FFFE,FFFF
$FFFC,FFFD
$FFFA,FFFB
SpecialTestorBootstrapVector
$BFFE,BFFF
$BFFC,BFFD
$BFFA,BFFB