MOTOROLA
6-2
CENTRAL PROCESSING UNIT
M68HC11
REFERENCE MANUAL
Figure 6-1 M68HC11 Programmer’s Model
Most operations can use accumulator A or B interchangeably; however, there are a
few notable exceptions. The ABX and ABY instructions add the contents of the 8-bit
accumulator B to the contents of the 16-bit index register X or Y, and there are no
equivalent instructions that use A instead of B. The TAP and TPA instructions are used
to transfer data from accumulator A to the condition code register or from the condition
code register to accumulator A; however, there are no equivalent instructions that use
B rather than A. The decimal adjust accumulator A (DAA) instruction is used after bi-
nary-coded decimal (BCD) arithmetic operations, and there is no equivalent BCD in-
struction to adjust B. Finally, the add, subtract, and compare instructions involving
both A and B (ABA, SBA, and CBA) only operate in one direction; therefore, it is im-
portant to plan ahead so the correct operand will be in the correct accumulator.
6.1.2 Index Registers (X and Y)
The 16-bit index registers X and Y are used for indexed addressing mode. In the in-
dexed addressing mode, the contents of a 16-bit index register are added to an 8-bit
offset, which is included as part of the instruction, to form the effective address of the
operand to be used in the instruction. In most cases, instructions involving index reg-
ister Y take one extra byte of object code and one extra cycle of execution time com-
pared to the equivalent instruction using index register X. The second index register is
especially useful for moves and in cases where operands from two separate tables are
involved in a calculation. In the earlier M6800 and M6801, the programmer had to
store the index to some temporary location so the second index value could be loaded
into the index register.
8-BIT ACCUMULATORS A & B
OR 16-BIT DOUBLE ACCUMULATOR D
7
15
0
7
0
0
A
B
D
IX
IY
SP
PC
7
0
C
V
Z
N
I
H
X
S
INDEX REGISTER X
INDEX REGISTER Y
STACK POINTER
PROGRAM COUNTER
CARRY/BORROW FROM MSB
OVERFLOW
ZERO
NEGATIVE
I-INTERRUPT MASK
HALF CARRY (FROM BIT 3)
X-INTERRUPT MASK
STOP DISABLE
CONDITION CODES