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參數(shù)資料
| 型號(hào)： | MC68HC11A8 |
| 廠商： | Motorola, Inc. |
| 元件分類： | 8位微控制器 |
| 英文描述： | 8-Bit Microcontroller(8位微控制器) |
| 中文描述： | 8位微控制器（8位微控制器） |
| 文件頁(yè)數(shù)： | 242/512頁(yè) |
| 文件大?。?/td> | 4071K |
| 代理商： | MC68HC11A8 |
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MOTOROLA
9-12
ASYNCHRONOUS SERIAL COMMUNICATIONS INTERFACE
M68HC11
REFERENCE MANUAL
interrupt requests; whereas, others simply indicate errors in the reception of a charac-
ter. These status bits are automatically set by the corresponding conditions having
been met in the SCI logic. Once set, these bits remain set until software completes a
clearing sequence. The clearing sequences are somewhat automatic in that they are
satisfied by performing functions normally done anyway. For example, to clear the
TDRE flag, software must read the SCSR while TDRE is set, and then write to the
TDR. Since these are exactly the normal steps in response to the TDRE, no instruc-
tions are needed to clear the flag.
TDRE — Transmit Data Register Empty
0 = Not empty; a character was previously written to the SCDR and has not yet
transferred to the transmit shift register to be serially sent.
1 = Indicates a new character may now be written to the SCDR.
In normal transmit operations, this bit is checked before each new character is sent to
see if the SCDR can accept the new data. The SCI transmitter is double buffered so
the TDR holds the second character in line while the transmit serial shift register holds
the character in the process of being transmitted serially. The TDRE flag is cleared by
reading SCSR, followed by a write to the SCDR. TDRE must be read as one during
the read of SCSR, or the first step of the clearing sequence is not satisfied. The TDRE
bit is set to one during reset to indicate that there is no meaningful data in the SCDR.
TC — Transmit Complete
0 = The transmitter is busy sending a character, preamble, or break character.
1 = The transmitter has completed sending and has reached an idle state.
This bit is useful in systems where the SCI is driving a modem. When TC is set at the
end of a transmission, the modem can be disabled. In older ACIA and SCI systems,
the TDRE status bit was the only indication that a transmission was near completion.
Since TDRE only indicated that the last character had transferred to the transmit shift
register, software had to delay an amount of time greater than or equal to the time it
took for this last character to finish transmitting serially. Since the delay time depended
on the baud rate, it was relatively difficult to know when it was safe to disable the mo-
dem. The TC bit on the M68HC11 offers a much more convenient way to tell when the
transmitter has completed sending. The TC flag is cleared by reading SCSR, followed
by a write to the SCDR. TC must be read as one during the read of SCSR, or the first
step of the clearing sequence is not satisfied. The TC bit is set to one during reset to
indicate that the transmitter is not busy transmitting anything.
RDRF — Receive Data Register Full
0 = Not full; nothing has been received since the last character was read out of the
SCDR.
1 = A character has been received and has transferred from the receive shift reg-
ister to the parallel SCDR where software can read it.
SCSR —
SCI Status Register
$102E
BIT 7
TDRE
1
6
5
4
3
2
1
BIT 0
0
0
TC
1
RDRF
0
IDLE
0
OR
0
NF
0
FE
0
RESET:
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