M68HC11
REFERENCE MANUAL
SYNCHRONOUS SERIAL PERIPHERAL INTERFACE
MOTOROLA
8-3
Figure 8-2 CPHA Equals One SPI Transfer Format
When CPHA equals zero, the SS line must be negated and reasserted between each
successive serial byte. Also, if the slave writes data to the SPI data register (SPDR)
while SS is active low, a write-collision error results.
When CPHA equals one, the SS line may remain active low between successive
transfers (can be tied low at all times). This format is sometimes preferred in systems
having a single fixed master and a single slave driving the MISO data line.
8.2 SPI Block Diagram
Figure 8-3
is a block diagram of the SPI subsystem. When an SPI transfer occurs, an
8-bit character is shifted out one data pin while a different 8-bit character is simulta-
neously shifted in a second data pin. Another way to view this transfer is that an 8-bit
shift register in the master and another 8-bit shift register in the slave are connected
as a circular 16-bit shift register. When a transfer occurs, this distributed shift register
is shifted eight bit positions; thus, the characters in the master and slave are effectively
exchanged.
The central element in the SPI system is the block containing the shift register and the
read data buffer. The system is single buffered in the transmit direction and double
buffered in the receive direction. This fact means new data for transmission cannot be
written to the shifter until the previous transaction is complete; however, received data
is transferred into a parallel read data buffer so the shifter is free to accept a second
serial character. As long as the first character is read out of the read data buffer before
the next serial character is ready to be transferred, no overrun condition will occur. A
single MCU register address is used for reading data from the read data buffer and for
writing data to the shifter.
Not defined but normally LSB of previously transmitted character.
6
5
4
3
2
1
LSB
6
5
4
3
2
1
LSB
2
3
4
5
6
7
8
1
MSB
MISO
(FROM SLAVE)
MOSI
(FROM MASTER)
SCK (CPOL=1)
SCK (CPOL=0)
SCK CYCLE #
(FOR REFERENCE)
SS (TO SLAVE)
MSB