
MOTOROLA
5-26
RESETS AND INTERRUPTS
M68HC11
REFERENCE MANUAL
be written once within the first 64 E-clock cycles after reset. IRQE is cleared by default
during reset.
The interrupt sources within the MCU all operate as a wired-OR level-sensitive net-
work. When an event triggers an interrupt, a software-accessible interrupt flag is set,
which (if enabled) causes a constant request for interrupt service. When software has
recognized the interrupt, this flag is cleared, thus releasing the request for service. The
flag bit acts as a static indication that service is required. If more than one interrupt
source is connected to a single level-sensitive line, the line may remain asserted for
several overlapping events from different sources, and the flag bits assure that all re-
quests will be serviced.
In an edge-sensitive network, the MCU is responsible for latching a request upon rec-
ognition of a low-going edge at the interrupt input. This configuration is only capable
of recognizing that an edge occurred (there is no software-accessible record to identify
the requesting source); thus, the edge-sensitive configuration is appropriate only
where a single source could have made the request.
5.6.2 Sharing Vector with Handshake I/O Interrupts
Because the IRQ vector is shared by the handshake I/O subsystem and the IRQ input
pin, the handshake I/O functions can be rebuilt externally when the MCU is operating
in expanded modes. While the MCU is in an expanded mode, 18 pins, which were
used for the handshake I/O subsystem, become dedicated to the expansion bus. The
MC68HC24 is a port replacement unit (PRU) that rebuilds the handshake I/O func-
tions. The MCU is specifically designed to treat the associated addresses as external
locations while in expanded modes so that software sees no difference between an
expanded system with a PRU and an M68HC11 operating in single-chip mode. Since
the handshake I/O system uses the same vector as the IRQ pin, the PRU can drive
the IRQ pin of the MCU. Even the interrupts for the handshake I/O system are faithfully
emulated.
The shared interrupt with IRQ solves most emulation problems for the PRU; however,
there are some difficulties in applications where IRQ is configured for edge-sensitive
operation. In such a system, the PRU is connected to the IRQ pin and to the user’s
external interrupt source. The edge-sensitive configuration is not able to distinguish
which source caused an interrupt. Also, if an edge-triggered interrupt is generated by
the external source while an interrupt is pending from the PRU, the low level on the
IRQ line prevents any new-edge from being detected. Since the level-sensitive config-
uration is more common for IRQ and since so many other pins can act as edge-sensi-
tive interrupt inputs, this limitation should not be serious.
5.7 Interrupts from Internal Peripheral Subsystems
The following paragraphs discuss common aspects of the interrupts generated by on-
chip peripheral systems. The interrupt sources for on-chip peripheral systems are dis-
cussed in greater detail in the sections for each peripheral system.