M68HC11
REFERENCE MANUAL
RESETS AND INTERRUPTS
MOTOROLA
5-11
Figure 5-1 Typical External Reset Circuit
5.3 Interrupt Process
The CPU in a microcontroller sequentially executes instructions. In many applications,
it is necessary to execute sets of instructions in response to requests from various pe-
ripheral devices. These requests are often asynchronous to the execution of the main
program. Interrupts provide a way to temporarily suspend normal program execution
so the CPU can be freed to service these requests. After an interrupt has been ser-
viced, the main program resumes as if there had been no interruption.
The instructions executed in response to an interrupt are called the interrupt service
routine. These routines are much like subroutines except that they are called through
the automatic hardware interrupt mechanism rather than by a subroutine call instruc-
tion, and all CPU registers are saved on the stack rather than just saving the program
counter. An interrupt (provided it is enabled) causes normal program flow to be sus-
pended as soon as the currently executing instruction finishes. The interrupt logic then
pushes the contents of all CPU registers onto the stack so the CPU context can be
restored after the interrupt is finished. After stacking the CPU registers, the vector for
the highest priority pending interrupt source is loaded into the program counter, and
execution continues with the first instruction of the interrupt service routine. An inter-
rupt is concluded with a return from interrupt (RTI) instruction, which causes all CPU
registers and the return address to be recovered from the stack so that the interrupted
program can resume as if there had been no interruption.
Interrupts can be enabled or disabled by mask bits (X and I) in the CCR and by local
enable mask bits in the on-chip peripheral control registers. A few important interrupt
sources that are always enabled are called non-maskable interrupts. The non-
maskable interrupt request (XIRQ) pin is effectively a non-maskable interrupt source
except that it is disabled immediately after reset. Very special logic is associated with
the interrupt mask bit (X) for XIRQ in the CCR to overcome classic problems associ-
ated with a non-maskable interrupt while allowing all of the benefits of such an inter-
rupt. The remaining interrupt sources are maskable by the interrupt mask bit (I) in the
4.7 k
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1
2
[4]
[3]
[2]
[1]
TO RESET
OF M68HC11
VDD
MC34064
GND
RESET
IN
RESET
GND
IN
MANUAL
RESET SWITCH
R1
C
MC34164
R2
VDD
VDD