
M68HC11
REFERENCE MANUAL
MAIN TIMER AND REAL-TIME INTERRUPT
MOTOROLA
10-41
half that belongs with the same count state as the upper half just read. Even though
the counter has actually advanced to n + 4 by the last cycle of this LDD instruction, the
value read will be the lower half of count n + 3.
The information in
Figure 10-13
and
Figure 10-14
can be combined to find the value
that would be returned if the LDD instruction was performed as the first instruction after
reset — that is, if the reset vector pointed directly to the LDD instruction. The value
read will always be $0005.
The prescaler is built around a divided by 16 counter. When a new value is written to
the prescaler control bits (PR1, PR0) in the TMSK2 register, the clocking rate to the
main timer changes to the new rate at the next $F–$0 transition of this internal 4-bit
prescaler counter.
Figure 10-15
shows timing details for an input capture. Input-capture timing is not af-
fected by a prescale factor; thus, this figure only shows the divided by one case. This
figure also only shows the case where the input-capture function is configured to de-
tect a rising edge. Again, the polarity of the edge is not important to the timing.
The normal sequence of events in an input capture is as follows:
1. Asynchronously detect an edge at the ICx pin.
2. Set the ICxF bit at the next falling edge of the internal PH2 clock.
3. Transfer the current timer count to the 16-bit TICx register during the next PH2
logic high.
Figure 10-15 Input-Capture Timing Details
If the cycle at [4] happens to be a high-byte read of the TlCx register (which would be
unusual), the transfer at [3] will be delayed until [6] so the transfer will not corrupt a
double-byte read at cycles [4] and [5].
Figure 10-16
shows two timing situations related to output compares. A normal com-
pare match is shown at [1]; a compare inhibit situation is shown at [4].
PH2
ICxF
E
TIMER COUNT
N 1
N+1
N
N+2
N+3
N+4
ICx PIN
READ TICx (HI)
READ TICx (LO)
[4]
[5]
[1]
[2]
[3]
[6]