M68HC11
REFERENCE MANUAL
PULSE ACCUMULATOR
MOTOROLA
11-9
trailing edge of a pulse so the PAIF service routine does not have to check for an over-
flow.
11.3.2 Configuring for Interrupt after a Specified Time
This concept is the time equivalent of setting up an interrupt after N events, which was
previously discussed. First, calculate the number of E divided by 64 counts, which
would be equivalent to the time period the user wants to specify. For example, if a de-
lay of 5 ms is desired, divide 5 ms by the time for one E divided by 64 count (from
Ta-
ble 11-1
, one count equals 32
μ
s for E = 2 MHz). Since 5 ms divided by 32
μ
s equals
156.25, truncate to 156. The resolution of the counter causes a tolerance of
±
32
μ
s
(64 E periods; E = 2 MHz). Next, take the two’s complement of this value and store the
result in the PACNT. When the input goes to its chosen active level, the counter will
start incrementing every 64 E cycles. An overflow will occur after the 156th count.
11.4 Other Uses for the PAI Pin
At any time, software can read the logic level on the PA7/PAI/OC1 pin even if one or
more of the other functions associated with this pin is also enabled. This pin can also
be used as an extra edge-triggered interrupt input pin when the pulse accumulator
functions are not needed. (In fact, examples have been presented in this chapter
where this pin is being used as an edge-triggered interrupt even while the pulse accu-
mulator is being used.) This pin has some advantages over the IRQ pin. The PEDGE
control bit allows the user to select either rising or falling edges (IRQ cannot be con-
figured to detect rising edges). The PAII control bit allows the user to locally enable or
disable this interrupt; in addition, the I bit in the CPU condition code register acts as a
global enable for all I-bit-related interrupts. Finally, the PAIF status flag allows software
to detect a pending PAI pin interrupt and to clear the pending interrupt if necessary
(with IRQ this function is not possible).
11.5 Timing Details for the Pulse Accumulator
The timing information presented in the following paragraphs is much more detailed
than most users will ever need. This information is not intended to replace guaranteed
datasheet timing information.
Figure 11-4
shows the timing related to edge detection at the PA7/PAI/OC1 pin. Pri-
marily, this timing concerns the event counting mode, but the setting of the PAIF status
flag applies to gated time accumulation mode as well. PAI signals are synchronized to
the internal phase 2 (PH2) clock to prevent any interference between clocking and
reading the PACNT. This synchronization process limits the maximum counting rate
for the pulse accumulator to one-half the E-clock frequency.
Any incoming edge [1] presented after the rising edge of E but before the next rising
edge of E is recognized during PH2 high and causes the PAIF status flag [2] to be set
at the falling edge of that PH2. In event counting mode, the PACNT counter is incre-
mented at that same PH2 falling edge. The soonest another edge can be detected is
two cycles later [3].