MOTOROLA
4-8
ON-CHIP MEMORY
M68HC11
REFERENCE MANUAL
to demonstrate the effect of programming both ones and zeros. Since the erased state
of an EEPROM bit is one, programming a one is the same as doing nothing. During
programming, the array ground is not driven. The control gates of the byte to be pro-
grammed are driven to zero through the row-select and column-select path. Control
gates for bytes not being programmed will be high impedance because the column-
select and/or row-select device will be off. The bit-select devices are turned on hard
because the row select, for the row containing the byte being programmed, is driven
to V
PP
. The bit lines are driven to V
DD
for bits not being programmed (ones) and to
V
PP
for bits being programmed (zeros).
For bits not being programmed (ones), the drain of the floating-gate transistor is at
V
DD
, and the control gate is at V
SS
. This configuration does not result in a large
enough field for tunneling to occur; thus, no charge transfer occurs.
Figure 4-6 Programming an EEPROM Byte
For bits being programmed (zeros), the drains of the floating-gate transistors are at
V
PP
– V
TN
(because of the drain-to-source threshold voltage drop across the bit-select
device), and the control gate is at V
SS
. This configuration results in a large enough field
so electrons can tunnel from the floating gate to the drain region of the floating-gate
transistor. Since the floating gate of a programmed bit has a positive charge, the float-
ing-gate transistor will conduct during reads.
Figure 4-7
shows an EEPROM byte being read. During a read operation, the bit lines
are precharged to one. Column selects enable the bit lines from the byte being read
to the sense amp inputs. The row select for the row containing the byte being read is
driven to V
DD
to enable the bit-select devices. The array ground is connected to V
SS
.
The floating gate devices of programmed bits conduct and pull the corresponding bit
lines to zero. The floating-gate devices of bits not programmed do not conduct; there-
fore, the corresponding bit lines remain at the precharged level and read as ones. EE-
PROM operations are actually much more complicated than this discussion suggests,
but the following general statements may be useful to designers using the EEPROM.
1) Since no high voltages are present during read operations, no degradation of data
ARRAY GROUND
(NOT DRIVEN)
7
VPP
6
5
4
3
2
1
0
VSS
0
1
0
1
0
1
0
1
VPP
VDD
VPP
VDD
VPP
VDD
VPP
VDD