M68HC11
REFERENCE MANUAL
PARALLEL INPUT/OUTPUT
MOTOROLA
7-41
the basis for data-sheet timing specifications so timing information can be extrapolated
for bus frequencies other than that used for the data sheet.
On a port E read, the RPORTE signal is asserted for one-fourth E-clock cycle to en-
able the pin input buffers and transfer the digital value from the port E pins into cross-
coupled NAND latches in the pin logic for each port E pin. The ATDREAD signal is also
asserted to enable transmission gates that couple the outputs of the NAND latches to
the internal data bus. Since the CPU does not actually use the data from the NAND
latches until after the RPORTE signal is disabled, the latches are actually acting as
synchronizers for port E data.
Figure 7-24 Idealized Port E Timing
7.4 Handshake I/O Subsystem
The handshake I/O subsystem involves ports B and C, STRA input, STRB output, and
the PIOC register. The following paragraphs explains the strobe and handshake pro-
tocols and the detailed operation of the PIOC register.
There are three primary modes of operation for the handshake I/O subsystem. The
first (default) mode of operation is the simple strobe mode, which uses port B as a sim-
ple strobe output port and port C as a simple latching input port. The second mode of
operation is a full-input handshake; the third mode is a full-output handshake. In the
full-handshake modes of operation, port B is not involved; therefore, it defaults to be-
ing a general-purpose output port.
If the application does not require handshake functions, these functions can generally
be ignored. Ports B and C can be used for simple general-purpose I/O; in fact, the
STRA and STRB pins can even be used for limited non-handshake functions. When
handshake functions are being used, it is usually possible to use any port C pins which
are not needed for handshake as general-purpose I/O pins, without interfering with the
handshake functions of the other port C pins. The one exception to this possibility is
that while full-output handshake is specified, port C pins cannot usually function as
general-purpose input pins. Examples of mixed use of port C pins is presented in
7.4.5
VALID DATA REQUIRED AT CPU
READ FROM PORT E
PH2 (INTERNAL)
EXTAL
AS
PORT E INPUT
RPORTE
ATDREAD
E