MOTOROLA
3-12
CONFIGURATION AND MODES OF OPERATION
M68HC11
REFERENCE MANUAL
Register Bits
.
A special register (TEST1) becomes accessible in the special modes. This register re-
verts to all zeros and cannot be written when SMOD is zero (normal modes). Other
than the DISR control bit in this register, the user should not be interested in the oper-
ation of these bits since they are only useful for factory testing of the MCU. Two other
control bits in the SCI baud-rate control register are similarly enabled only in the spe-
cial modes.
3.5.1 Testing Functions Control Register (TEST1)
The following register and paragraphs discuss the TEST1 control register. Testing
functions are not recommended for use by the user since they may change at any time
to meet the manufacturing requirements of Motorola; however, brief descriptions of
these testing functions will be presented. Occasionally, knowledge of these functions
will help a user understand what is happening if one of these functions is accidentally
invoked during development of an application.
*The DISR control bit resets to one in special modes.
TILOP — Test Illegal Opcode
Can be written only while SMOD equals one
1 = Enable illegal opcode testing function
0 = Function disabled
In factory test equipment, information presented to the data bus pins is independent
of the address coming from the MCU. In normal systems, the address outputs from the
MCU enable a specific location in a memory device so the data presented to the MCU
is specifically related to the address. The TILOP works in conjunction with the LIR pin
to allow testing of illegal opcodes on consecutive bus cycles rather than requiring the
time-consuming interrupt service normally associated with illegal opcodes. One con-
sequence of the implementation of this function is that the address bus begins to dec-
rement after the first illegal opcode is detected at the data bus. Since there is no
cause-effect relationship between address and data on the factory test equipment, this
unusual address bus activity poses no difficulty for factory testing of illegal opcodes.
However, this unusual address bus activity makes the illegal opcode test function un-
usable in a normal system.
OCCR — Output Condition Code Register Status to Timer Port
Can be written only while SMOD equals one
1 = The condition code register bits (H, N, Z, V, and C) are driven out of the five
most significant bits of port A (bits [7:3], respectively), which allows the CPU op-
eration to be verified without the burden of complex branching routines.
NOTE
TEST1 —
Testing Functions Control Register
$103E
BIT 7
TILOP
0
6
0
0
5
4
3
2
1
BIT 0
TCON
0
OCCR
0
CBYP
0
DISR
0*
FCM
0
FCOP
0
RESET: