參數(shù)資料
型號: M32000D3FP
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 66.6 MHz, RISC MICROCONTROLLER, PQFP100
封裝: 14 X 20 MM, 0.65 MM PITCH, PLASTIC, LQFP-100
文件頁數(shù): 73/155頁
文件大?。?/td> 1340K
代理商: M32000D3FP
2-4
M32000D3FP User's Manual
CPU
2.3 Control registers
2.3.1 Processor status word register: PSW (CR0)
The processor status word register (PSW) shows the M32R CPU status. It consists of the current PSW
field, and the BPSW field where a copy of the PSW field is saved when EIT (For details, refer to Chapter 4
"EIT".) occurs.
The PSW field is made up of the stack mode bit (SM), the interrupt enable bit (IE) and the condition bit
(C).
The BPSW field is made up of the backup stack mode bit (BSM), the backup interrupt enable bit (BIE) and
the backup condition bit (BC).
D
bit name
function
init.
R
W
16
BSM (backup SM)
saves value of SM bit when EIT occurs
undefined
17
BIE (backup IE)
saves value of IE bit when EIT occurs
undefined
23
BC (backup C)
saves value of C bit when EIT occurs
undefined
24
SM (stack mode)
0: uses R15 as the interrupt stack pointer
0
1: uses R15 as the user stack pointer
25
IE (interrupt enable)
0: does not accept interrupt
0
1: accepts interrupt
31
C (condition bit)
indicates carry, borrow and overflow resulting
0
from operations (instruction dependent)
16 17
23 24 25
31
15
8
7
0
SM
IE
C
BC
BSM
BIE
0
PSW
BPSW field
PSW field
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