參數(shù)資料
型號: M32000D3FP
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 66.6 MHz, RISC MICROCONTROLLER, PQFP100
封裝: 14 X 20 MM, 0.65 MM PITCH, PLASTIC, LQFP-100
文件頁數(shù): 127/155頁
文件大?。?/td> 1340K
代理商: M32000D3FP
M32000D3FP User's Manual
INTERNAL MEMORY AND MEMORY CONTROLLER
5-7
5.3 Cache memory
(4) Purge
When the CP bit of the cache control register (MCCR) is set to "1", the cache memory is purged.
Purge is inseparably performed, and accesses to the cache memory cannot be accept until the purge
completion.
purge in internal instruction/data cache mode
Whether reconstitution to the internal DRAM for whole lines of the cache memory is necessary (the
Dirty bit of the tag section is set to "1") is checked, and every line involved is written back, then
all the lines are nullified (the Valid bit of the tag section is zero-cleared). A period of 512 to 2304
internal clock cycles is necessary to complete purging.
purge in instruction cache mode
In instruction cache mode, the Dirty bit of the tag section is not checked, and all the lines are
nullified (the Valid bit of the tag section is zero-cleared) without reconstitution. A period of 256
internal clock cycles is necessary to finish purging.
(5) Access time from the M32R CPU
The clock cycles necessary to access from the M32R CPU to the memory system vary depending
on whether a cache hit or a cache miss occurs, or on whether a page of the internal DRAM is hit
or missed.
Refer to Appendix 3 "Instruction execution time" for execution time under individual conditions.
Fig. 5.3.2 Access time from the M32R CPU
CPU access
read
write
DRAM page hit
DRAM page miss
cache hit
cache miss
cache hit
cache miss
cache-off
Since the write buffer is built-in, the
operation viewed from the M32R CPU
seems to be similar except when
successive access is made.
DRAM page hit
DRAM page miss
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