參數(shù)資料
型號： M32000D3FP
元件分類： 微控制器/微處理器
英文描述： 32-BIT, 66.6 MHz, RISC MICROCONTROLLER, PQFP100
封裝： 14 X 20 MM, 0.65 MM PITCH, PLASTIC, LQFP-100
文件頁數(shù)： 138/155頁
文件大小： 1340K
代理商： M32000D3FP
M32000D3FP User's Manual
EXTERNAL BUS INTERFACE
6-3
6.1 Bus interface unit (BIU)
6.1.2 External bus master access operations
When an external bus master accesses the internal DRAM, a hold request is input to the M32000D3FP;
_____
when this is accepted, address information, control signals and the CS signal are input. The BIU accesses
the internal DRAM via the memory controller according to these control signals input by the external bus
master.
When accessing consecutive addresses within the 128-bit boundary, the BIU buffers the transfer data a
maximum of 8 times, and minimizes the number of internal data transfers.
(1) External bus master read operation
When reading the internal DRAM from an external bus master, 128-bit data including the address
read from the internal DRAM is read in batch into the BIU’s data buffer. Then, data is output in 16-
bit units based on the address information and control signals.
In internal instruction/data cache mode, the BIU reads data from the cache memory, only if there is
requested data in the cache memory (cache hit). In the case of a cache miss, data is read directly
from the internal DRAM without a copy to the cache memory taking place.
(2) External bus master write operation
When writing to the internal DRAM from the external bus master, data is first accumulated in the
BIU’s 128-bit data buffer and then written to the internal DRAM when the accessed address exceeds
the 128-bit boundary.
When an external bus master is writing and a cache hit occurs, data is written into the cache memory
only. When a cache miss occurs, data is written to the internal DRAM only without a write to cache
memory taking place.
Fig. 6.1.2 External bus master access operations
128-bit
internal data bus
external data bus
(16 bits)
M32000D3FP
BIU
128-bit
data bus buffer
(bus width conversion)
external bus master read with cache hit in internal instruction/data cache mode
, maximum 8 times burst read
cache
memory
DRAM
CPU
, maximum 8 times burst write
external bus master read with other than
external bus master write with cache hit in internal instruction/data cache mode
external bus master write with other than
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