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參數(shù)資料
| 型號(hào)： | M32000D3FP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 66.6 MHz, RISC MICROCONTROLLER, PQFP100 |
| 封裝： | 14 X 20 MM, 0.65 MM PITCH, PLASTIC, LQFP-100 |
| 文件頁(yè)數(shù)： | 54/155頁(yè) |
| 文件大小： | 1340K |
| 代理商： | M32000D3FP |
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M32000D3FP User's Manual
APPENDICES
A-5
Appendix C Instruction execution time
The number of the memory access cycles for the IF and MEM stages are shown below. The given values
are the minimum number of cycles and the values below and actual operation may vary.
For example, in write access, the M32R CPU only writes in the write buffer, therefore operation completes
in the MEM stage. However, actually writing in memory occurs thereafter. Instruction execution time may be
larger than the theoretical values, depending on the memory and bus state before and after when the M32R
CPU requests the memory access.
R (read cycle)
number of cycles (min.)
when in instruction queue ................................................................ 1
when cache hit occurs ..................................................................... 1
when cache miss occurs
internal DRAM page hit ...................................................... 4 (see note 1)
internal DRAM page miss ................................................... 8 (see note 1)
when in cache off mode
internal DRAM page hit ...................................................... 4 (see note 1)
internal DRAM page miss ................................................... 8 (see note 1)
when reading external memory (byte, halfword) .......................... 10 (see note 2)
when reading external memory (word) .......................................... 14 (see note 2)
W (write cycle)
number of cycles (min.)
when cache hit occurs ..................................................................... 2 (see note 3)
when cache miss and write to internal DRAM ............................. 2 (see note 3)
when in cache off mode and write to internal DRAM ................. 2 (see note 3)
when write to external memory ....................................................... 2 (see note 3)
Notes 1: A page hit occurs when bit 12 to 22 of address are the same for the internal DRAM and
when re-access occurs within 1024 cycles of the internal clock.
2: When the external memory access occurs with no-wait state. Because the internal and
external clock frequency of the M32R CPU differ, this value varies according to the access
request timing from the M32R CPU.
3: Since the write buffer is built-in, the operation viewed from the M32R CPU seems to be
similar except when successive access is made.
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