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參數(shù)資料
| 型號： | M32000D3FP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 66.6 MHz, RISC MICROCONTROLLER, PQFP100 |
| 封裝： | 14 X 20 MM, 0.65 MM PITCH, PLASTIC, LQFP-100 |
| 文件頁數(shù)： | 140/155頁 |
| 文件大?。?/td> | 1340K |
| 代理商： | M32000D3FP |
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M32000D3FP User's Manual
EXTERNAL BUS INTERFACE
6-5
6.2 External bus interface related signals
___
(7) Read/write (R/W)
___
The M32000D3FP outputs a R/W signal to identify whether the external bus cycle is a read or write
___
operation. When accessing the internal DRAM from an external bus master, a R/W signal is input
from the system bus side.
read bus cycle:
___
R/W = "H"
write bus cycle:
___
R/W = "L"
____________
(8) Burst (BURST)
The M32000D3FP drives two consecutive bus cycles to access 32-bit data located on the 32-bit
boundary. In instruction fetching, it drives a maximum of 8 (fixed to 8 cycles in instruction cache
mode) consecutive read cycles to access data located on the 128-bit boundary. While driving these
____________
consecutive bus cycles, the M32000D3FP outputs "L" level to BURST.
When accessing 32-bit data, the address of the MSB-side 16 bits are output before the address of
the LSB side 16 bits. When accessing 128-bit data, the addresses are output for every access cycle
from the arbitrary 16-bit aligned addresses to wraparound within the 128-bit boundary.
___
(9) Data complete (DC)
_____
When starting an external bus cycle, the M32000D3FP automatically inserts wait cycles until the DC
_____
signal is input from external. Wait control using the DC signal is effective also for bus cycles during
burst transfer.
_____
When the M32000D3FP is in the hold state and if the CS signal is input, the M32000D3FP outputs
_____
the DC signal to notify the external bus master that internal DRAM access is complete.
__________
(10) Hold control (HREQ, HACK)
The hold state is the state when the external bus access stops and all pins go to a high-impedance
state. However, the internal DRAM can be accessed while the external bus is in the hold state.
__________
To put the M32000D3FP into the hold state, input an "L" level to HREQ.
When the hold request is accepted and the M32000D3FP enters the hold state, an "L" level is output
__________
from HACK.
Table 6.2.1 Pin condition in hold state
pin name
pin condition or operation
____
A8 - A30, SID, BCH, BCL,
high-impedance
__
___ _______
ST, R/W, BS, BURST
D0 - D15
output when internal DRAM is read by an external bus master
___
__
(CS = "L", R/W = "H"), otherwise high-impedance
__
DC
output when internal DRAM is accessed by an external bus master
___
(CS = "L"), otherwise high-impedance
_____
HACK
output "L"
other pins
normal operation
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