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參數(shù)資料
| 型號： | M32000D3FP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 66.6 MHz, RISC MICROCONTROLLER, PQFP100 |
| 封裝： | 14 X 20 MM, 0.65 MM PITCH, PLASTIC, LQFP-100 |
| 文件頁數(shù)： | 2/155頁 |
| 文件大?。?/td> | 1340K |
| 代理商： | M32000D3FP |
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1-2
OVERVIEW
M32000D3FP User's Manual
1.1 Performance overview
The M32000D3FP belongs to the M32R/D series in the M32R family.
1.1.1 M32R family CPU
(1) RISC architecture
The M32R family CPU (abbreviated to the M32R CPU) has a RISC architecture. Memory is accessed
by load/store instructions and other operations are executed by register-to-register operation instructions.
It has sixteen 32-bit general-purpose registers. 83 instructions are implemented.
In addition to load/store instructions, the M32R CPU supports compound instructions such as "load
& address update", and "store & address update". These are useful for high-speed data transfer.
(2) 5-stage pipeline processing
The M32R CPU executes instructions using 5-stage pipeline processing: instruction fetch, decode,
execute, memory access and write back. It executes not only load instructions, store instructions
and register-to-register operation instructions, but also compound instructions, such as load &
address update and store & address update, in 1 cycle.
Instructions are put into the execute stage in the order in which they are fetched, however, if the
execution of a previously loaded load instruction or store instruction has been delayed because of
a memory access wait cycle being inserted, the next register operation instruction is in some cases
executed first. The M32R CPU controls instruction execution without wasting clock cycles by "out-
of-order-completion" or other processing methods.
(3) Compacted instruction codes
The M32R CPU instructions have two formats: 16-bit length and 32-bit length. A 16-bit length
instruction format can reduce the program code size.
With the 32-bit length instructions, it is possible to directly branch within a range of
±32 MB from
the address of the instruction being executed. This makes programming easier compared to the
case of an architecture with a segmented address space.
1.1.2 Built-in multiply-accumulate function
(1) Internal high-speed multiplier
The M32R CPU has a internal 32-bit x 16-bit high-speed multiplier which enables execution of 32-
bit x 32-bit integer multiplication operations in 3 cycles (1 cycle is 15 ns when internally operating
at 66.6 MHz).
(2) Multiply-accumulate instructions giving DSP-like functionality
Using 56 bits of the accumulator, the M32R CPU supports the following 4 multiply-accumulate
instructions (or multiply instructions). All instructions can be executed in 1 cycle.
- high-order 16 bits of register x high-order 16 bits of register
- low-order 16 bits of register x low-order 16 bits of register
- all 32 bits of register x high-order 16 bits of register
- all 32 bits of register x low-order 16 bits of register
The M32R CPU has an instruction to round values stored in the accumulator to 16 or 32 bits, and
an instruction to shift and store in a register so as to align the accumulator values. Because these
instructions are executed in 1 cycle, when used with high-speed data transfer instructions, such as
load & address update and store & address update, a data processing capability matching DSP
functionality is exhibited.
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