參數(shù)資料
型號(hào): M32000D3FP
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 66.6 MHz, RISC MICROCONTROLLER, PQFP100
封裝: 14 X 20 MM, 0.65 MM PITCH, PLASTIC, LQFP-100
文件頁數(shù): 147/155頁
文件大?。?/td> 1340K
代理商: M32000D3FP
M32000D3FP User's Manual
EXTERNAL BUS INTERFACE
6-11
6.4 Burst access operation
When the cache memory operation mode is the instruction cache mode, and burst reading of the
instructions within the 128-bit boundary for cache replacement occurs, the bus cycle is driven a
fixed 8 times from an arbitrary 32-bit boundary address and to wraparound within the 128-bit
boundary.
When other than the instruction cache mode is selected and burst reading a set of instructions of
less than 128 bits, consecutive bus cycles are driven from an arbitrary 32-bit boundary address
as the top to the 128-bit line (A28 to A30 = "111") .
Fig. 6.4.2 4-word (128-bit) burst read timing (1-0-0-0-0-0-0-0 wait)
Wait cycles can be inserted even when burst transferring by setting DC = "H".
"H"
idle
CLKIN
BS
A8 - A30
SID, ST
BCH, BCL
BURST
D0 - D15
DC
R/W
burst read ( 4 words)
idle
"Hi-z"
Note: "Hi-z" means high-impedance, and
indicates sampling timing.
Keep DC signal to at the "H" level during idle cycles.
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