參數(shù)資料
型號(hào): M32000D3FP
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 66.6 MHz, RISC MICROCONTROLLER, PQFP100
封裝: 14 X 20 MM, 0.65 MM PITCH, PLASTIC, LQFP-100
文件頁數(shù): 129/155頁
文件大?。?/td> 1340K
代理商: M32000D3FP
M32000D3FP User's Manual
INTERNAL MEMORY AND MEMORY CONTROLLER
5-9
5.4 Internal memory configuration and cache mode
5.4.2 Instruction cache mode
When the instruction cache mode is selected, the cache functions as an instruction cache for the internal
DRAM or the external memory, and caching is carried out for instruction fetch access. This mode is
designed for use when an external ROM is used as program memory and the internal DRAM is used as
data memory, or when instructions are located in the internal DRAM.
When instruction codes in the user space are overwritten by the external bus master or an other source,
instruction code coherency in the cache memory is not guaranteed. Furthermore, caching is not applied
when accessing the internal DRAM from the external bus master.
Fig. 5.4.2 Instruction cache mode
external bus
(16 bits)
16
external bus
interface
M32000D3FP
128
instruction
cache
BIU
128
DRAM
CPU
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