參數(shù)資料
型號: M32000D3FP
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 66.6 MHz, RISC MICROCONTROLLER, PQFP100
封裝: 14 X 20 MM, 0.65 MM PITCH, PLASTIC, LQFP-100
文件頁數(shù): 124/155頁
文件大小: 1340K
代理商: M32000D3FP
5-4
M32000D3FP User's Manual
INTERNAL MEMORY AND MEMORY CONTROLLER
5.3 Cache memory
The M32000D3FP has a 4K-byte cache memory.
5.3.1 Characteristics of cache memory
The cache memory is configured as:
cache capacity: 4K bytes
operation mode: selectable from the following three modes
- internal instruction/data cache mode
- instruction cache mode
- cache-off mode
mapping method: direct mapping
main memory updating method: copy back method
line size: 128 bits (16 bytes)
The M32000D3FP’s internal cache memory has a capacity of 128 bits (16 bytes) x 256 entries - 4K bytes
in total. The tag memory section within the cache memory is made up of a 20-bit tag address, a Valid bit,
and a Dirty bit.
The Valid bit is set to "1" when data stored in the cache memory is valid. The Dirty bit is set to "1" when
data stored is overwritten, which indicates that reconstitution of the internal DRAM is necessary either by
replacing the cache or by purging the cache.
The data section within the cache memory is of 128-bit (16-byte) width, and is connected to M32000D3FP’s
internal 128-bit bus. Therefore, all cache operations are performed on data in units of 128 bits.
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