參數(shù)資料
型號： M32000D3FP
元件分類： 微控制器/微處理器
英文描述： 32-BIT, 66.6 MHz, RISC MICROCONTROLLER, PQFP100
封裝： 14 X 20 MM, 0.65 MM PITCH, PLASTIC, LQFP-100
文件頁數(shù)： 41/155頁
文件大?。?/td> 1340K
代理商： M32000D3FP
ELECTRICAL CHARACTERISTICS
M32000D3FP User's Manual
12-7
12.4 AC characteristics
(3) arbitration and external bus master read/write timing
symbol
parameter
test
limits
unit
reference
conditions
number
min.
max.
td(CLKIN-HACKHX)
____
HACK = "H" effective time after CLKIN
0
ns
42
td(CLKIN-HACKL)
____
HACK = "L" delay time after CLKIN
12
ns
43
td(CLKIN-HACKLX)
____
HACK = "L" effective time after CLKIN
0
ns
44
td(CLKIN-HACKH)
____
HACK = "H" delay time after CLKIN
12
ns
45
td(CLKIN-AZ)
address output disable time after CLKIN
16
ns
46
td(CLKIN-AZX)
address output enable time after CLKIN
0
ns
47
td(CLKIN-DZX)
data output enable time after CLKIN
0
ns
54
td(CLKIN-DV)
data output delay time after CLKIN
18
ns
55
td(CLKIN-DXZ)
data output disable time after CLKIN
16
ns
56
td(CLKIN-DVX)
data output effective time after CLKIN
0
ns
57
td(CS-DCZX)
__
DC output enable time after CS
0
ns
58
td(CLKIN-DCHX)
__
DC = "H" effective time after CLKIN
0
ns
59
td(CLKIN-DCL)
__
DC = "L" delay time after CLKIN
16
ns
60
td(CLKIN-DCXZ)
__
DC output disable time after CLKIN
16
ns
61
td(CLKIN-DCLX)
__
DC = "L" effective time after CLKIN
0
ns
62
(4) standby timing
symbol
parameter
test
limits
unit reference
conditions
number
min.
max.
td(CLKIN-STBYHX)
____
STBY = "H" effective time after CLKIN
0
ns
65
td(CLKIN-STBYL)
____
STBY = "L" delay time after CLKIN (see note)
tc(CLKIN)n/4 + 15
ns
66
td(CLKIN-STBYLX)
____
STBY = "L" effective time after CLKIN
0
ns
67
td(CLKIN-STBYH)
____
STBY = "H" delay time after CLKIN (see note)
tc(CLKIN)n/4 + 15
ns
68
_____
Note: The STBY signal is synchronized with the internal clock, therefore its timing changes at 0, 90, 180 and 270
(n=0, 1, 2, 3) degree phase of CLKIN.
(5) I/O port timing
symbol
parameter
test
limits
unit
reference
conditions
number
min.
max.
tw(PORTOUTL) port output "L" pulse width (see note)
12
ns
71
tw(PORTOUTH) port output "H" pulse width (see note)
12
ns
72
Note: The minimum pulse width value is that where the output is changed within 1 clock of the internal clock. Software
processing time to write to the port data register is not included.
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