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參數(shù)資料
| 型號： | M32000D3FP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 66.6 MHz, RISC MICROCONTROLLER, PQFP100 |
| 封裝： | 14 X 20 MM, 0.65 MM PITCH, PLASTIC, LQFP-100 |
| 文件頁數(shù)： | 56/155頁 |
| 文件大?。?/td> | 1340K |
| 代理商： | M32000D3FP |
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M32000D3FP User's Manual
APPENDICES
A-7
s Notes on designing the circuit for the internal PLL
(1) PLLCAP pin
The value of the capacitor connected to the PLLCAP pin should be as near as possible to the
recommended value. Mount it as near as possible the PLLCAP pin. The other end should be connected
to ground near the PLLVSS pin.
(2) De-coupling capacitor for oscillation stability improvement
Oscillation stability will be improved when a de-coupling capacitor is placed between the PLLVCC pin
and the PLLVSS pin. Use a device such as 0.1
F multilayer ceramic capacitor, which is superior
at high frequency, for the de-coupling capacitor and put it as near to both pins as possible.
(3) Board pattern design consideration for oscillation stability improvement
When designing PCB circuit patterns, factors to reduce the common impedance of PLLVSS and VSS
to improve oscillation stability should be considered. For example, separate the tracks to PLLVCC
and PLLVSS coming from the power source from those feeding other VCC and VSS pins. Also use
the shortest and broadest tracks possible. Better still, we recommend the use of separate power and
ground layers in the PCB to reduce the total impedance of the whole electrical system
s Notes on designing peripheral circuits common to M32000D3FP (internal 1M-byte DRAM version)
and M32000D4AFP (internal 2M-byte DRAM version)
M32000D3FP (internal 1M-byte DRAM version) and M32000D4AFP (internal 2M-byte DRAM version) are
pin compatible in consideration of drop in replacement depending on system configuration, however, two
___
of the functions, those of the SID pin and the DC pin, are different. Notes for use in designing M32000D3FP
(and M32000D4AFP) external circuits like the peripheral ASICs are shown below.
Appendix D Notes
Table D.1 Notes for designing peripheral circuits common to M32000D3FP and M32000D4AFP
M32000D3FP
M32000D4AFP
notes
(internal DRAM 1M bytes)
(internal DRAM 2M bytes)
SID pin
input an "L" level when
access from external
design so as to input an "L"
accessing internal DRAM
devices to internal DRAM
level for the M32000D3FP
from external devices
is ignored (Don't care)
when accessing internal
DRAM from external devices
___
DC pin
input an "H" level to the
___
DC pin state is ignored
design so as to input an "H"
___
DC pin during idle cycles
during idle cycles
level for the M32000D3FP
(Don't care)
during idle cycles
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相關(guān)代理商/技術(shù)參數(shù) |
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| M32002AGMJ | 制造商:MTRONPTI 制造商全稱:MTRONPTI 功能描述:9x14 mm, 3.3/2.5/1.8 Volt, PECL/LVDS/CML, VCXO |
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