參數(shù)資料
型號: M32000D3FP
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 66.6 MHz, RISC MICROCONTROLLER, PQFP100
封裝: 14 X 20 MM, 0.65 MM PITCH, PLASTIC, LQFP-100
文件頁數(shù): 66/155頁
文件大?。?/td> 1340K
代理商: M32000D3FP
1-10
OVERVIEW
M32000D3FP User's Manual
1.3 Pin function
Table 1.3.1 Pin function (3/3)
type
pin name
name
I/O
function
bus
___
DC
data complete
I/O
When the M32000D3FP drives an external bus cycle,
control
(Hi-z)*
___
it automatically inserts wait cycles until DC is input
(cont.)
by the slave device in the system bus.
When the M32000D3FP is in the hold state and the
internal DRAM is accessed from an external bus master,
___
the M32000D3FP outputs DC to notify to the external
bus master that the bus cycle to the internal DRAM
has been completed.
_____
HREQ
hold
input
Bus right request input pin of the system bus. When
_____
HREQ is an "L" level, the M32000D3FP switches to
the hold state.
_____
HACK
hold
output
Indicates that the M32000D3FP has switched to the
acknowledge
hold state and releases the bus right of the system
bus to the requestor.
___
CS
chip
input
Signal input to the M32000D3FP when it is in the hold
select
state to request access to the internal DRAM from an
external access to the internal DRAM from an external
___
bus master. When an "L" level is input to CS, the
M32000D3FP accesses the internal DRAM at the
address input via the address pins.
interrupt
___
SBI
system
input
System break interrupt input pin. The SBI is not masked
controller
break
by the IE bit in the PSW register. It is also used to
interrupt
return from CPU sleep mode and to request the start
of operation in slave mode.
___
INT
external
input
External interrupt request input pin. It is also used to
interrupt
return from CPU sleep mode and to request the start
of operation the slave mode.
programm-
PP0, PP1
port
I/O
Two programmable I/O ports.
able I/O port
* (Hi-z): This pin goes to high-impedance in the hold state.
___
__
** The DC pin becomes an output pin when the CS signal is input to the M32000D3FP.
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