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參數(shù)資料
| 型號： | M32000D3FP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 66.6 MHz, RISC MICROCONTROLLER, PQFP100 |
| 封裝： | 14 X 20 MM, 0.65 MM PITCH, PLASTIC, LQFP-100 |
| 文件頁數(shù)： | 13/155頁 |
| 文件大?。?/td> | 1340K |
| 代理商： | M32000D3FP |
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M32000D3AFP User's Manual
OVERVIEW
1-3
1.1 Performance overview
1.1.3 Internal large capacity DRAM and cache memory
(1) Internal DRAM
An internal 8M-bit (1 MB) DRAM is included in the M32000D3FP.
In addition to a 32-bit RISC CPU core, 1 MB DRAM and 4 KB cache memory, the M32000D3FP
has on-chip peripheral functions such as a memory controller.
The M32000D3FP consists of a CPU and memory integrated on a single-chip.
Because the I/O controller is externally located, the M32000D3FP can be used in a wide range of
applications as an advanced general-purpose microcomputer.
A 3-chip configuration of the M32000D3FP, ASIC as a peripheral controller, and a program ROM,
enables variable applications such as data processing or equipment control.
(2) 128-bit internal bus and high-speed operation
The CPU, internal DRAM and cache memory are connected by an 128-bit internal bus. Data
transfer from the DRAM to cache memory and from cache memory to the CPU are executed in 128-
bit units, and instruction and data transfer between the CPU and internal DRAM is carried out at
high-speed.
The CPU and internal bus operate at 66.6 MHz (max.). As a result, the M32000D3FP achieves a
high 52.4 VAX MIPS performance, based on the Dhrystone V2.1 benchmark test, when using the
internal DRAM and operating at 66.6 MHz.
Bottlenecks which form between the CPU and memory in von Neumann computers have been
eliminated by the wide internal bus, the internal DRAM, and high operating frequency.
(3) Incorporates high-performance technology
The M32000D3FP contains all resources required by conventional RISC microcomputers such as
external high-speed memory or a complex memory control circuit.
(4) Lower power consumption achieved using a 16-bit external bus
A 16-bit data and a 24-bit address bus are the M32000D3FP's external bus and interfaces with
external peripheral controllers. The external bus operating frequency is 16.65 MHz (max.).
By incorporating the DRAM in the microcomputer, the bottlenecks which occur between a microcomputer
and memory have been eliminated and external bus data traffic is kept comparatively low.
A narrower external data bus and lower transfer speed have decreased the power requirement of
the external bus drivers, thus bringing down overall power consumption.
The M32000D3FP external bus interface has an 128-bit buffer that supports burst transfer mode.
Using this, the data transfer speed from external ROM to the cache memory and from the internal
DRAM to external devices is accelerated.
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