參數(shù)資料
型號: M32000D3FP
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 66.6 MHz, RISC MICROCONTROLLER, PQFP100
封裝: 14 X 20 MM, 0.65 MM PITCH, PLASTIC, LQFP-100
文件頁數(shù): 32/155頁
文件大?。?/td> 1340K
代理商: M32000D3FP
M32000D3FP User's Manual
OSCILLATION CIRCUIT
11-3
11.3 Oscillation stabilization period
In the M32000D3FP oscillation multiplier circuit, an unstable oscillation period may occur immediately after
___
power on or on returning from standby mode. In order to stabilize PLL oscillation, the "L" level input to RST
_____
and WKUP should last a minimum of 2 ms after the clock input to CLKIN stabilizes and VCC stabilizes at
the specified voltage level.
Fig. 11.3.1 Oscillation stabilization period
VCC
RST
CLKIN
VCC
RST or
WKUP
internal clock
CLKIN
internal clock
power on
power source
stabilization
period
oscillation stabilization period (see note 1)
clock input restating
CLKIN stop period
(see note 2)
oscillation stabilization period (see note 3)
Notes 1:
2:
3:
Input reset signal for a minimum of 2 ms after CLKIN input and VCC stabilize.
Input clock can be stopped when the M32000D3FP is in standby mode. During this time,
the internal DRAM data are retained by refresh operation using a dedicated free-run timer.
When the clock input restarts, input an "L" level to RST or WKUP for more than 2 ms after
CLKIN input stabilizes to allow for oscillation stabilization time.
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