參數(shù)資料
型號: M32000D3FP
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 66.6 MHz, RISC MICROCONTROLLER, PQFP100
封裝: 14 X 20 MM, 0.65 MM PITCH, PLASTIC, LQFP-100
文件頁數(shù): 141/155頁
文件大小: 1340K
代理商: M32000D3FP
6-6
M32000D3FP User's Manual
EXTERNAL BUS INTERFACE
6.2 External bus interface related signals
___
(11) Internal DRAM access control (CS)
_____
The internal DRAM can be accessed when CS is driven to an "L" level after the M32000D3FP enters
__________
the hold state (HACK = "L").
To access the internal DRAM from external, the following signals from the system bus side should
be controlled.
A8 to A30
Input internal DRAM addresses to be read or written.
_______
BCH, BCL
_______
Specify the byte position of data to be written into the internal DRAM. BCH corresponds to the
_______
MSB side (D0 to D7), and BCL corresponds to the LSB side (D8 to D15).
__
R/W
___
Specify read or write operation. When reading, R/W = "H". When writing, R/W = "L".
D0 to D15
16-bit data I/O bus.
SID
When accessing the internal DRAM from an external bus master, an "L" level is input to SID to
specify user space.
_____
DC
This signal notifies to an external bus master that the internal DRAM access is complete. When
_____
access is complete, an "L" level is output to DC.
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