參數(shù)資料
型號: M32000D3FP
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 66.6 MHz, RISC MICROCONTROLLER, PQFP100
封裝: 14 X 20 MM, 0.65 MM PITCH, PLASTIC, LQFP-100
文件頁數(shù): 154/155頁
文件大?。?/td> 1340K
代理商: M32000D3FP
6-18
M32000D3FP User's Manual
EXTERNAL BUS INTERFACE
6.6 External bus master access
6.6.3 External bus master read/write cycle
___
When the external bus master makes an access, the value of the R/W signal that controls the data direction
___
of the bus interface cannot be changed during CS = "L". Therefore, read cycles and write cycles cannot
___
be mixed while CS = "L".
When starting a write cycle following after a read cycle and starting a read cycle following a write cycle,
___
keep the CS signal at an "H" level for at least 1 CLKIN.
Fig. 6.6.3 Read/write bus cycle to internal DRAM
CLKIN
HREQ
BCH, BCL
D0 - D15
DC
R/W
hold shift
hold
return
HACK
A8 - A30
CS
("L" output)
read
CS = "H"
write
("L" output)
SID
("L" input)
"Hi-z"
V
"Hi-z"
Note: "Hi-z" means high-impedance, and
indicates sampling timing.
Also, where marked above with V, keep CS signal to "H" at least 1 CLKIN when
starting a write bus cycle after a read bus cycle or a read bus cycle after a write
bus cycle.
"Hi-z"
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