參數(shù)資料
型號: M32000D3FP
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 66.6 MHz, RISC MICROCONTROLLER, PQFP100
封裝: 14 X 20 MM, 0.65 MM PITCH, PLASTIC, LQFP-100
文件頁數(shù): 109/155頁
文件大?。?/td> 1340K
代理商: M32000D3FP
M32000D3FP User's Manual
EIT
4-21
4.10 Trap processing
4.10.1 Trap (TRAP)
[Occurrence condition]
The trap is a software interrupt which is generated by executing the TRAP instruction. A total of 16
traps are available and specified by operands 0 to 15 of the TRAP instruction 16 matching EIT vector
entries are available.
[EIT processing]
(1) SM, IE and C bits saving
The SM, IE and C bits are saved in the PSW register.
BSM
← SM
BIE
← IE
BC
← C
(2) SM, IE and C bits updating
The SM, IE and C bits are updated.
SM
← not changed
IE
← 0
C
← 0
(3) PC saving
When a TRAP instruction is executed, "PC value in the TRAP instruction + 4" is set in the BPC.
For example, if the TRAP instruction is in address 4, "8" is set in the BPC. If it is address 6, then
"10" is set. In this case, the value of bit 30 in the BPC indicates whether the TRAP instruction that
caused the trap is within the word boundary (BPC[30] = 0) or not (BPC[30] = 1).
In both of the above cases, however, the return address of the RTE instruction after EIT handler
processing is completed becomes address 8 because the lowest 2 bits are cleared to "00" when
returning the BPC value to the PC.
When a program is created with a standard Mitsubishi assembler, the assembler automatically
inserts an NOP instruction to the halfword immediately following a TRAP instruction located on the
word boundary.
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