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參數(shù)資料
| 型號： | M32000D3FP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 66.6 MHz, RISC MICROCONTROLLER, PQFP100 |
| 封裝： | 14 X 20 MM, 0.65 MM PITCH, PLASTIC, LQFP-100 |
| 文件頁數(shù)： | 11/155頁 |
| 文件大?。?/td> | 1340K |
| 代理商： | M32000D3FP |
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8-4
M32000D3FP User's Manual
POWER MANAGEMENT FUNCTION
8.2 Standby mode
8.2.2 Bus state in standby mode
__________
In standby mode, the STBY signal goes to "L" level to indicate that the M32000D3FP is in standby mode.
It retains the bus state as it was immediately before switching.
Table 8.2.1 Pin condition at standby mode
pin name
when state immediately
before was idle
before was hold
A8 - A30, SID, ST
output undefined
high-impedance
____
__
___
______
BCH, BCL, R/W, BS, BURST
output "H"
high-impedance
__
D0 - D15, DC
high-impedance
_____
HACK
output "H"
output "L"
_____
STBY
output "L"
other pins
retain state as it was
immediately before switching
8.2.3 Returning from standby mode
__________
_______
Input an "L" level to WKUP or RST to return from standby mode to normal operation mode. The contents
____
in the internal DRAM are retained upon return using the WKUP signal.Table 8.2.2 shows the internal state
_________
of the M32000D3FP after it returns from standby mode on input of the WKUP signal.
__________
(1) Return by WKUP signal input
__________
The return operation using the WKUP signal is the same as that for a reset, except that the contents
of the internal DRAM and the MPMR are retained. When the M32000D3FP is set to master mode
__________
and the WKUP signal is input, execution restarts from the reset vector entry. When the M32000D3FP
is set to slave mode, it does not execute the instruction fetch operation to the reset vector entry.
_____
Instead, it waits for an "L" level input to level to INT or SBI and then starts operation by an instruction
fetch to the corresponding interrupt vector entry.
__________
If the M32000D3FP is returned to normal operation following a WKUP signal input then the contents
of MPMR are retained. After using this as an input factor recognition flag for the reset interrupt
handler, PM0 and PM1 should be cleared to "00". The contents of the MPMR are retained until they
are cleared by the reset interrupt handler, however, the M32000D3FP will not switch to CPU sleep
mode again until PM0 and PM1 are once more set to "11".
It is not guaranteed that the device will switch to standby mode or CPU sleep mode again without
first clearing PM0 and PM1 to "00" on return from standby mode. Please ensure this operation is
implemented.
________
(2) Return by RST signal input
________
The return operation using the RST signal is the same as that of a normal reset. The M32000D3FP
is initialized internally (the MPMR is cleared to "00") and the contents of the internal DRAM are not
retained.
However, when the M32000D3FP is set to slave mode rather than normal mode, it does not execute
the instruction fetch operation to the reset vector entry as per a normal mode reset. Instead, it waits
_____
for an "L" level input to INT or SBI and then starts operation by an instruction fetch to the corresponding
interrupt vector entry.
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