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參數(shù)資料
| 型號： | M32000D3FP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 66.6 MHz, RISC MICROCONTROLLER, PQFP100 |
| 封裝： | 14 X 20 MM, 0.65 MM PITCH, PLASTIC, LQFP-100 |
| 文件頁數(shù)： | 17/155頁 |
| 文件大小： | 1340K |
| 代理商： | M32000D3FP |
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M32000D3FP User's Manual
POWER MANAGEMENT FUNCTION
8-9
8.3 CPU sleep mode
8.3.3 Returning from CPU sleep mode
______
_______
When an INT, SBI or RST signal is input to the M32000D3FP, the state returns to normal operation mode.
______
If the M32000D3FP is returned to normal operation following an INT or an SBI signal input then the
contents of MPMR are retained. After using these as an input factor recognition flag for the external
interrupt handler or the SBI handler, PM0 and PM1 should be cleared to "00". The contents of the MPMR
are retained until they are cleared by the external interrupt handler, however, the M32000D3FP will not
switch to CPU sleep mode again until PM0 and PM1 are once more set to "10".
It is not guaranteed that the device will switch to standby mode or CPU sleep mode again without first
clearing
PM0 and PM1 to "00" on return from CPU sleep mode. Please ensure this operation is
implemented.Table 8.3.2 shows the internal state of the M32000D3FP after it returns from CPU sleep mode
_____
on input of the INT or SBI signal.
______
(1) Return using INT signal input
The clock supply to the M32R CPU restarts after two internal clocks from when the "L" level is input
______
to INT. Upon return using the INT signal, the contents shown below are retained and the same
processing as with the EI in normal operation mode is carried out.
cache memory
internal DRAM
general-purpose registers
internal I/O control register
______
If an external interrupt is masked (the IE bit in the PSW register is "0") when the INT signal is input,
execution starts from the program state immediately before switching to CPU sleep mode and the EI
processing is not carried out.
______
(2) Return using SBI signal input
The clock supply to the M32R CPU restarts after two internal clocks from when an "L" level is input
______
to SBI. Upon return using the SBI signal, the contents shown below are retained.
cache memory
internal DRAM
general-purpose registers
internal I/O control register
Because the SBI cannot be masked, the SBI processing as per normal operation mode is carried out.
______
The SBI is used when some problem has occurred within the system, such as a break in power
______
source or an error indicated by an external watchdog timer. Use the INT or RST signal to return from
______
CPU sleep mode, and limit the use SBI only to emergency situations.
______
(3) Return using RST signal input
______
The return operation carried out by using the RST signal is the same as that following a normal reset.
The M32000D3FP is initialized internally and the contents of the internal DRAM are not retained.
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