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參數(shù)資料
| 型號(hào)： | M32000D3FP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 66.6 MHz, RISC MICROCONTROLLER, PQFP100 |
| 封裝： | 14 X 20 MM, 0.65 MM PITCH, PLASTIC, LQFP-100 |
| 文件頁數(shù)： | 132/155頁 |
| 文件大?。?/td> | 1340K |
| 代理商： | M32000D3FP |
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5-12
M32000D3FP User's Manual
INTERNAL MEMORY AND MEMORY CONTROLLER
D
bit name
function
R
W
24 - 30
Not assigned.
0
x
31
LM (lock mode)
______
0: HREQ exclusive lock mode
___
1: CS exclusive lock mode
5.5 Memory controller
(1) Lock control register (MLCR) <address: H'FFFF FFF7>
D24
25
26
27
28
29
30
D31
LM
The lock mode is selected by the lock control register (MLCR). While the M32000D3FP is locked
__________
(from the execution of a LOCK instruction until the execution of an UNLOCK instruction), the HREQ
_____
input or CS input cannot be accessed. This functionality is used to manage exclusive accesses to
common resources in multi-CPU systems.
The following two lock modes can be selected by the LM (lock mode) bit.
______
HREQ exclusive lock mode (LM = "0")
__________
When the LM bit is set to "0", the M32000D3FP enters the HREQ exclusive lock mode. In this
__________
mode, HREQ inputs are not accepted while the M32000D3FP is locked (HACK signal is not
returned); the external bus master cannot use the external bus to access the M32000D3FP internal
DRAM.
__________
If the M32000D3FP is already in the hold state (HACK = "L"), the M32R CPU delays executing the
__________
LOCK instruction until the hold is released (HACK = "H" by HREQ = "H").
Always set this mode when using the M32000D3FP in master mode (external accessing mode).
___
CS exclusive lock mode (LM = "1")
_____
When the LM bit is set to "1", the M32000D3FP enters the CS exclusive lock mode. In this mode,
_____
the CS input is not accepted while the M32000D3FP is locked (DC signal is not returned).
_____
While the internal DRAM is being accessed by a bus master (CS = "L"), the M32R CPU delays
_____
executing the LOCK instruction until the access completes (CS = "H").
Only access to the M32000D3FP internal DRAM from an external bus master is prohibited in this
mode. Even while the M32000D3FP is locked, a hold request from an external bus master can be
accepted.
This mode should only be used when the M32000D3FP is in slave mode (when the external bus
is not used by the M32000D3FP).
In master mode, if an access from the external bus master to the internal DRAM in the locked
_____
M32000D3FP is in the DC wait state, and then the locked M32000D3FP accesses external space,
a dead lock state is entered (the only means to exit this state is by a hardware reset.).
<at reset: H'00>
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