參數(shù)資料
型號: M32000D3FP
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 66.6 MHz, RISC MICROCONTROLLER, PQFP100
封裝: 14 X 20 MM, 0.65 MM PITCH, PLASTIC, LQFP-100
文件頁數(shù): 7/155頁
文件大?。?/td> 1340K
代理商: M32000D3FP
7-6
M32000D3FP User's Manual
MASTER/SLAVE MODE
7.3 Master/slave system configuration example
(2) Common bus coprocessor configuration
In this configuration, the slave M32000D3FP can also access the external bus. Communications between
the master and slave CPUs is carried out using the programmable I/O ports and the interrupt request input.
The following are data transaction methods.
When the slave M32000D3FP is in the hold state, the master M32000D3FP accesses the internal
DRAM in the slave M32000D3FP.
When the slave M32000D3FP outputs the hold request to the master M32000D3FP and the master
M32000D3FP is in the hold state, the system bus is accessed. It is also possible to access the
internal DRAM in the master M32000D3FP.
M32000D3FP
(master)
ROM
ASIC
PP0
M/S
HREQ
INT
M32000D3FP
(slave)
HACK
HREQ
HACK
bus
arbiter
INT
Fig. 7.3.2 Common bus coprocessor configuration
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