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| 型號： | M32000D3FP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 66.6 MHz, RISC MICROCONTROLLER, PQFP100 |
| 封裝： | 14 X 20 MM, 0.65 MM PITCH, PLASTIC, LQFP-100 |
| 文件頁數(shù)： | 105/155頁 |
| 文件大?。?/td> | 1340K |
| 代理商： | M32000D3FP |
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M32000D3FP User's Manual
EIT
4-17
4.9 Interrupt processing
4.9.3 System break interrupt (SBI)
______
The SBI is an interrupt request from the SBI pin. It is not masked by the IE bit in the PSW register. It is
used in the case that some problem has already occurred until the system when the interrupt is detected,
such as a break in power source or an error from an external watchdog timer. In this case, use of the SBI
is under the condition that after SBI handler processing, control does not return to the original program that
was executing when the SBI occurred.
Furthermore, the SBI and the EI also have the following two functions.
To return the M32000D3FP to normal operation mode from CPU sleep mode.
For details, refer to Chapter 8 "Power management function".
To start the M32000D3FP when in slave mode after a reset or after returning from standby mode.
For details, refer to Chapter 7 "Master/slave modes".
In both of the above cases, use the EI and limit the use of the SBI only to emergency situations such as
a system breakdown.
[Occurrence condition]
______
The SBI occurs when an "L" level is input to the SBI pin. In normal operation mode, the M32R CPU
______
checks the SBI pin at the instruction break point on the word boundary. The SBI pin is continously
checked when the M32000D3FP is in CPU sleep mode, or when starting the M32000D3FP after reset
______
or after returning from standby mode. In this case, if an "L" level is input to the SBI pin, the SBI is
accepted (The SBI is not masked by the IE bit in the PSW register.).
The SBI does not start immediately after a 16-bit instruction on the word boundary is executed
(However, with a 16-bit branch instruction, the SBI is accepted immediately after branching.).
______
Note: Because the M32R CPU checks the SBI pin at the instruction break point on the word
boundary, an "L" level signal should be input continuously when a request is made when in
normal mode. In the case shown below, however, the interrupt request is always accepted
______
when an "L" level signal of 1 CLK width is input to the SBI pin, because the SBI pin is
continuously monitored under the following conditions:
after reset in slave mode
after returning from standby mode in slave mode
returning from CPU sleep mode.
16-bit instruction
instruction execution sequence
32-bit instruction
1000
1002
1004
1008
interrupt
accept
O.K.
interrupt
accept
No
16-bit instruction
address
interrupt
accept
O.K.
interrupt
accept
O.K.
Fig. 4.9.1 System break interrupt (SBI) accept timing
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