參數(shù)資料
型號: M32000D3FP
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 66.6 MHz, RISC MICROCONTROLLER, PQFP100
封裝: 14 X 20 MM, 0.65 MM PITCH, PLASTIC, LQFP-100
文件頁數(shù): 149/155頁
文件大小: 1340K
代理商: M32000D3FP
M32000D3FP User's Manual
EXTERNAL BUS INTERFACE
6-13
6.5 Bus arbitration
__________
When an "L" level is input to HREQ, the M32000D3FP switches to the hold state and outputs an "L" level
__________
to HACK. While the M32000D3FP is in the hold state, bus related pins go to a high-impedance state, and
data transfer is carried out on the system bus.
__________
To return to normal operation mode from the hold state, the HREQ signal should be changed to an "H" level.
Fig. 6.5.1 Bus arbitration timing
"Hi-z"
(see note 2)
"Hi-z"
Notes 1: Before switching to the hold state, an idle cycle of 1 CLKIN clock period is always inserted.
After returning from the hold state, an idle cycle of 1 to 5 CLKIN clock periods is always inserted.
2: "Hi-z" means high-impedance, and
indicates sampling timing.
3: While the M32000D3FP is in the hold state, the DC signal is driven and output when the CS signal
is input.
(see note 2)
(see note 3)
write
CLKIN
HREQ
BCH, BCL
D0 - D15
DC
R/W
idle
hold shift
hold
return
idle
HACK
A8 - A30
SID, ST
(see note 1)
BS
BURST
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