參數(shù)資料
型號(hào): M32000D3FP
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 66.6 MHz, RISC MICROCONTROLLER, PQFP100
封裝: 14 X 20 MM, 0.65 MM PITCH, PLASTIC, LQFP-100
文件頁數(shù): 53/155頁
文件大?。?/td> 1340K
代理商: M32000D3FP
M32000D3FP User's Manual
A-4
APPENDICES
Appendix C Instruction execution time
The instruction execution time of each pipeline stage is shown below. The E stage is considered as representing
the instruction execution time, however, because of pipeline processing, the execution times for other stages
may effect the total instruction execution time. In particular, the IF (instruction fetch), D (decode), and E
(execution) stages of the subsequent instruction should be considered after a branch has occurred.
The table shows the number of the instruction execution cycles for each pipeline stage in the M32000D3FP.
Refer to "M32R family software manual" for detail of pipeline processing.
Notes 1: R, W: Refer to the next page.
2: If the addressing mode of the store instructions is register indirect and register update, 1 cycle
is needed for the WB stage.
Table C.1 Instruction execution cycles in each stage
number of execution cycles in each stage (see note 1)
instruction
IF
D
E
MEM
WB
load instruction (LD, LDB, LDUB, LDH, LDUH, LOCK)
R
1
R
1
store instruction (ST, STB, STH, UNLOCK)
R
1
W
(1) (see note 2)
multiply instruction (MUL)
R
1
3
-
1
divide/reminder instruction (DIV, DIVU, REM, REMU)
R
1
37
-
1
other instructions
R
1
-
1
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