參數(shù)資料
型號(hào): M32000D3FP
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 66.6 MHz, RISC MICROCONTROLLER, PQFP100
封裝: 14 X 20 MM, 0.65 MM PITCH, PLASTIC, LQFP-100
文件頁數(shù): 122/155頁
文件大?。?/td> 1340K
代理商: M32000D3FP
M32000D3FP User's Manual
INTERNAL MEMORY AND MEMORY CONTROLLER
5-3
5.2 Internal DRAM
The M32000D3FP has an 8M-bit (1M-byte) DRAM.
5.2.1 Page mode for the internal DRAM
The M32000D3FP has a 1M-byte DRAM that supports page mode. Successive access to in-page addresses
(areas for which A12 through A22 are the same) results in a page hit; up to 16 bytes (128 bits) when
fetching an instruction or up to 4 bytes (32 bits) when reading/writing data are accessed in only four
internal clock cycles (when an operation frequency is 66.6 MHz, one internal clock cycle is 15 ns). Exceeding
the page boundary results in a page miss, and access is made in eight internal clock cycles.
5.2.2 Internal DRAM refresh operation
Either in normal operation mode or in CPU sleep mode, refresh is CAS-before-RAS type. Refresh is
performed every 1024 internal clock cycles and the internal bus is occupied for 8 internal clock cycles.
Arbitration between refresh and access is fully under control of the built-in memory controller. In standby
mode, self-refresh is performed by a built-in free run timer so that the internal DRAM’s contents are maintained.
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