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| 型號： | M32000D3FP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 66.6 MHz, RISC MICROCONTROLLER, PQFP100 |
| 封裝： | 14 X 20 MM, 0.65 MM PITCH, PLASTIC, LQFP-100 |
| 文件頁數(shù)： | 126/155頁 |
| 文件大小： | 1340K |
| 代理商： | M32000D3FP |
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5-6
M32000D3FP User's Manual
INTERNAL MEMORY AND MEMORY CONTROLLER
5.3 Cache memory
5.3.2 Cache memory operation
Achieving high-speed access, either data or instructions the M32R CPU accessed is taken to the cache
memory. The cache memory’s operations are shown below. All of these operations are carried out in terms
of 128 bits, which is the line size.
Regardless of modes, the cashing operations are applied to the user space (SID = 0) of the internal cache
memory. The I/O space (SID = 1) is not.
(1) Taking data or instructions in the cache memory
Either data or instructions the M32R CPU read is taken to the cache memory. In internal instruction/
data cache mode, the caching operation is applied to all read access to the internal DRAM; in
instruction cache mode, the caching operation is applied to any instruction fetch access to the user
space. Access from the external bus master is not applied.
(2) Operation when writing
If an attempt is made to write to data not on the cache memory (write cache miss), no change is
made in the cache memory though either the internal DRAM or external memory is directly overwritten.
If an attempt is made to write to data taken in the cache memory (write cache hit), one of the
following operations is performed depending on the mode selected then.
write cache hit in internal instruction/data cache mode
Only the data on the cache memory are updated; data on the internal DRAM will not be updated
until they are replaced or purged (the copy back method is used).
write cache hit in instruction cache mode
Data either on the internal DRAM or on external memory are directly overwritten, though data on
the cache memory are not updated. No nullification is made either (The Valid bit of the tag section
is being set to "1"). For this reason, if a program is changed, the cache memory has to be definitely
purged so as to cause data either on the internal DRAM or on external memory to take effect.
(3) Replacement algorithm
Taking to the cache memory, the line to be stored has been fixed in advance depending on A20
through A27, which correspond to the line address (the direct mapping method is used). When
replacement is performed, taking new data in the line on which effective data have already been
existed.
Replacement in internal instruction/data cache mode
Whether the write back of the line involved is necessary (the Dirty bit of the tag section is "1") is
checked, and the line involved is written back if necessary to take in new data. If not necessary,
(the Dirty bit of the tag section is "0"), no reconstitution is made to take in new data.
Replacement in instruction cache mode
In instruction cache mode, the Dirty bit of the tag section is not checked, and no reconstitution is
made to take in new data.
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