參數(shù)資料
型號: M32000D3FP
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 66.6 MHz, RISC MICROCONTROLLER, PQFP100
封裝: 14 X 20 MM, 0.65 MM PITCH, PLASTIC, LQFP-100
文件頁數(shù): 151/155頁
文件大?。?/td> 1340K
代理商: M32000D3FP
M32000D3FP User's Manual
EXTERNAL BUS INTERFACE
6-15
6.6 External bus master access
Fig. 6.6.1 Read bus cycle to internal DRAM
("L" output)
("L" input)
"Hi-z"
V
HREQ
BCH, BCL
D0 - D15
DC
R/W
hold shift
hold
return
HACK
A8 - A30
CS
read
SID
Note: "Hi-z" means high-impedance, and
indicates sampling timing.
CLKIN
The value of the R/W signal that controls the data direction of the bus interface
cannot be changed during CS="L". Hold this value while CS="L".
Also, where marked above with V, 3 to 7 CLKIN clock periods are necessary for
the first read operation (also when reading crosses an 128-bit boundary) when
reading from the internal DRAM. Hold the input value of the address or other control
signals during these wait cycle periods (DC = "H"). Consecutive read operations
within an 128-bit boundary are completed in 1 CLKIN clock period.
During these wait cycle periods, CS cannot be returned to an "H" level (the access
cannot be aborted). CS can only be returned to an "H" level after DC is driven to "L".
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